{"id":"https://openalex.org/W2005724636","doi":"https://doi.org/10.1109/40.42987","title":"Analog VLSI synaptic matrices as building blocks for neural networks","display_name":"Analog VLSI synaptic matrices as building blocks for neural networks","publication_year":1989,"publication_date":"1989-12-01","ids":{"openalex":"https://openalex.org/W2005724636","doi":"https://doi.org/10.1109/40.42987","mag":"2005724636"},"language":"en","primary_location":{"id":"doi:10.1109/40.42987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/40.42987","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068275012","display_name":"O. Rossetto","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"O. Rossetto","raw_affiliation_strings":["National Polytechnic Institute of Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Polytechnic Institute of Grenoble, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055562421","display_name":"Christian Jutten","orcid":"https://orcid.org/0000-0002-4477-4847"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C. Jutten","raw_affiliation_strings":["National Polytechnic Institute of Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Polytechnic Institute of Grenoble, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110454159","display_name":"J. H\u00e9rault","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Herault","raw_affiliation_strings":["National Polytechnic Institute of Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Polytechnic Institute of Grenoble, France","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078954494","display_name":"I. Kreuzer","orcid":null},"institutions":[{"id":"https://openalex.org/I200332995","display_name":"TU Dortmund University","ror":"https://ror.org/01k97gp34","country_code":"DE","type":"education","lineage":["https://openalex.org/I200332995"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"I. Kreuzer","raw_affiliation_strings":["University of Dortmund, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Dortmund, Germany","institution_ids":["https://openalex.org/I200332995"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.0967,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.96164978,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"9","issue":"6","first_page":"56","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7986544370651245},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6715927720069885},{"id":"https://openalex.org/keywords/content-addressable-memory","display_name":"Content-addressable memory","score":0.6614606976509094},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6089572310447693},{"id":"https://openalex.org/keywords/associative-property","display_name":"Associative property","score":0.5856450796127319},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5629462599754333},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5405150651931763},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48500964045524597},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2783997058868408},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.24153584241867065},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.16925173997879028},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1460382044315338},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08790937066078186},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07712045311927795}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7986544370651245},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6715927720069885},{"id":"https://openalex.org/C53442348","wikidata":"https://www.wikidata.org/wiki/Q745101","display_name":"Content-addressable memory","level":3,"score":0.6614606976509094},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6089572310447693},{"id":"https://openalex.org/C159423971","wikidata":"https://www.wikidata.org/wiki/Q177251","display_name":"Associative property","level":2,"score":0.5856450796127319},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5629462599754333},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5405150651931763},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48500964045524597},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2783997058868408},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.24153584241867065},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.16925173997879028},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1460382044315338},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08790937066078186},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07712045311927795},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/40.42987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/40.42987","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321694","display_name":"Instituto Polit\u00e9cnico Nacional","ror":"https://ror.org/059sp8j34"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W23758216","https://openalex.org/W1512944870","https://openalex.org/W1516319240","https://openalex.org/W1523020892","https://openalex.org/W1560672376","https://openalex.org/W1564953322","https://openalex.org/W1995341919","https://openalex.org/W2024330324","https://openalex.org/W2065758324","https://openalex.org/W2096108938","https://openalex.org/W2136166259","https://openalex.org/W2173317357","https://openalex.org/W2594453830","https://openalex.org/W3036512766","https://openalex.org/W6630830659","https://openalex.org/W6631058716"],"related_works":["https://openalex.org/W2077804929","https://openalex.org/W2046912830","https://openalex.org/W2098218272","https://openalex.org/W1974468537","https://openalex.org/W1540514728","https://openalex.org/W1984090010","https://openalex.org/W2107697999","https://openalex.org/W2049114128","https://openalex.org/W279701215","https://openalex.org/W1902246517"],"abstract_inverted_index":{"An":[0],"associative":[1],"memory":[2],"circuit":[3],"that":[4],"may":[5],"let":[6],"designers":[7],"expand":[8],"neural":[9],"networks":[10],"around":[11],"a":[12],"matrix":[13],"of":[14,21,53,61],"analog":[15],"synapses":[16,63],"is":[17],"described.":[18],"The":[19],"architecture":[20],"the":[22,43,48,54,71],"chip":[23],"and":[24,30,37,50,64],"its":[25],"basic":[26],"cell":[27],"are":[28,35,73],"discussed,":[29],"some":[31],"SPICE":[32],"simulation":[33],"results":[34],"presented":[36],"compared":[38],"with":[39],"measures":[40],"provided":[41],"by":[42],"first":[44],"prototype.":[45],"In":[46],"particular,":[47],"linearity":[49],"dynamic":[51],"response":[52],"complete":[55],"chip,":[56],"which":[57],"includes":[58],"an":[59],"array":[60],"25":[62],"two":[65],"address":[66],"decoders":[67],"used":[68],"for":[69],"programming":[70],"weights,":[72],"examined.<":[74],"<ETX":[75],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[76],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[77]},"counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}