{"id":"https://openalex.org/W2180025811","doi":"https://doi.org/10.1109/4.881211","title":"A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme","display_name":"A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme","publication_year":2000,"publication_date":"2000-11-01","ids":{"openalex":"https://openalex.org/W2180025811","doi":"https://doi.org/10.1109/4.881211","mag":"2180025811"},"language":"en","primary_location":{"id":"doi:10.1109/4.881211","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.881211","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051802399","display_name":"S. Atsumi","orcid":"https://orcid.org/0009-0003-7397-7701"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"S. Atsumi","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109463028","display_name":"Akira Umezawa","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"A. Umezawa","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066755966","display_name":"T\u00f4ru Tanzawa","orcid":"https://orcid.org/0000-0001-8228-2520"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Tanzawa","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110670014","display_name":"T. Taura","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Taura","raw_affiliation_strings":["Memory Division, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory Division, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027720906","display_name":"H. Shiga","orcid":"https://orcid.org/0009-0004-4626-3647"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Shiga","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056722782","display_name":"Yoshimichi Takano","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Takano","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003554905","display_name":"T. Miyaba","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Miyaba","raw_affiliation_strings":["Advanced LSI Technology Development Department, Toshiba Microelectronics Corporation, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Advanced LSI Technology Development Department, Toshiba Microelectronics Corporation, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031084193","display_name":"M. Matsui","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Matsui","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088389427","display_name":"Hiroshi Watanabe","orcid":"https://orcid.org/0000-0002-6742-1913"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Watanabe","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019839445","display_name":"K. Isobe","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Isobe","raw_affiliation_strings":["Micro and Custom LSI Division, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Micro and Custom LSI Division, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018186507","display_name":"S. Kitamura","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Kitamura","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020653533","display_name":"Shigeru Yamada","orcid":"https://orcid.org/0000-0002-7085-703X"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Yamada","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060219659","display_name":"M. Saito","orcid":"https://orcid.org/0000-0002-4754-8263"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Saito","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079451508","display_name":"Seiichi Mori","orcid":"https://orcid.org/0000-0001-8569-4504"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Mori","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111961771","display_name":"T. Watanabe","orcid":null},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Watanabe","raw_affiliation_strings":["Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Memory LSI Research and Development Center, Toshiba Semiconductor Company Limited, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":15,"corresponding_author_ids":["https://openalex.org/A5051802399"],"corresponding_institution_ids":["https://openalex.org/I1292669757"],"apc_list":null,"apc_paid":null,"fwci":3.1479,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.91870909,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"35","issue":"11","first_page":"1648","last_page":"1654"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/eeprom","display_name":"EEPROM","score":0.9362994432449341},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.690737783908844},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6376041173934937},{"id":"https://openalex.org/keywords/eprom","display_name":"EPROM","score":0.5999899506568909},{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.5545710325241089},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.5209544897079468},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4858545958995819},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4588963985443115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44587400555610657},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.4411185383796692},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43877556920051575},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4120585322380066},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.36263012886047363},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3563101887702942},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3226706385612488},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.23938927054405212},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2157614529132843},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.11601722240447998},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07054859399795532}],"concepts":[{"id":"https://openalex.org/C27699510","wikidata":"https://www.wikidata.org/wiki/Q205908","display_name":"EEPROM","level":2,"score":0.9362994432449341},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.690737783908844},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6376041173934937},{"id":"https://openalex.org/C163980746","wikidata":"https://www.wikidata.org/wiki/Q378210","display_name":"EPROM","level":2,"score":0.5999899506568909},{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.5545710325241089},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.5209544897079468},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4858545958995819},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4588963985443115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44587400555610657},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.4411185383796692},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43877556920051575},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4120585322380066},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.36263012886047363},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3563101887702942},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3226706385612488},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.23938927054405212},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2157614529132843},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.11601722240447998},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07054859399795532},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.881211","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.881211","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1500177473","https://openalex.org/W1534193085","https://openalex.org/W1571486900","https://openalex.org/W1585145541","https://openalex.org/W1921858828","https://openalex.org/W2038735426","https://openalex.org/W2063381451","https://openalex.org/W2065502355","https://openalex.org/W2103303987","https://openalex.org/W2117093682","https://openalex.org/W2128490237","https://openalex.org/W2145603583","https://openalex.org/W2148392146","https://openalex.org/W2162922645","https://openalex.org/W2535148590","https://openalex.org/W2789160415","https://openalex.org/W4246512415"],"related_works":["https://openalex.org/W2140342184","https://openalex.org/W2543283504","https://openalex.org/W2053998373","https://openalex.org/W4236860293","https://openalex.org/W2155969782","https://openalex.org/W2538429361","https://openalex.org/W1979028768","https://openalex.org/W1871359013","https://openalex.org/W1559405705","https://openalex.org/W2129481704"],"abstract_inverted_index":{"A":[0,18,43,59],"1.8-V-only":[1],"32-Mb":[2],"NOR":[3],"flash":[4],"EEPROM":[5],"has":[6,21,52,91],"been":[7,22,53,72,92],"developed":[8,73],"based":[9],"on":[10],"the":[11,34,56],"0.25-/spl":[12,39],"mu/m":[13,40],"triple-well":[14],"double-metal":[15],"CMOS":[16,41],"process.":[17],"channel-erasing":[19,57],"scheme":[20,63],"implemented":[23],"to":[24,74],"realize":[25],"a":[26,48,65],"cell":[27],"size":[28],"of":[29,85],"0.49":[30],"/spl":[31],"mu/m/sup":[32],"2/,":[33],"smallest":[35],"yet":[36],"reported":[37],"for":[38,55],"technology.":[42],"block":[44],"decoder":[45],"circuit":[46],"with":[47],"novel":[49],"erase-reset":[50],"sequence":[51],"designed":[54],"operation.":[58],"bitline":[60],"direct":[61],"sensing":[62],"and":[64],"wordline":[66],"boosted":[67],"voltage":[68],"pooling":[69],"method":[70],"have":[71],"obtain":[75],"high-speed":[76],"reading":[77],"operation":[78],"at":[79,88],"low":[80],"voltage.":[81],"An":[82],"access":[83],"time":[84],"90":[86],"ns":[87],"1.8":[89],"V":[90],"realized.":[93]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
