{"id":"https://openalex.org/W2149778532","doi":"https://doi.org/10.1109/4.760383","title":"A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors","display_name":"A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors","publication_year":1999,"publication_date":"1999-05-01","ids":{"openalex":"https://openalex.org/W2149778532","doi":"https://doi.org/10.1109/4.760383","mag":"2149778532"},"language":"en","primary_location":{"id":"doi:10.1109/4.760383","doi":"https://doi.org/10.1109/4.760383","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.760383","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021465692","display_name":"Fabian Klass","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Klass","raw_affiliation_strings":["Sun Microsyst. Inc., Palo Alto, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sun Microsyst. Inc., Palo Alto, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066552989","display_name":"C. Amir","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C. Amir","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"A. Das","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Das","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021045457","display_name":"Kathirgamar Aingaran","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Aingaran","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"C. Truong","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C. Truong","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082116755","display_name":"R. Wang","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Wang","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113501328","display_name":"A. Mehta","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Mehta","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074984237","display_name":"R. Heald","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Heald","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5016161583","display_name":"Gin Yee","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G. Yee","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":7.1182,"has_fulltext":false,"cited_by_count":158,"citation_normalized_percentile":{"value":0.9739604,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"34","issue":"5","first_page":"712","last_page":"716"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9916999936103821,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9916999936103821,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0052999998442828655,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0006000000284984708,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flops","display_name":"flip-flops","score":0.7789999842643738},{"id":"https://openalex.org/keywords/dynamic-circuits","display_name":"dynamic circuits","score":0.9739999771118164},{"id":"https://openalex.org/keywords/edge-triggered-flip-flop","display_name":"edge-triggered flip-flop","score":0.9150000214576721},{"id":"https://openalex.org/keywords/embedded-logic","display_name":"embedded logic","score":0.8090000152587891},{"id":"https://openalex.org/keywords/single-phase-clock","display_name":"single-phase clock","score":0.7509999871253967},{"id":"https://openalex.org/keywords/synchronization","display_name":"synchronization","score":0.597000002861023},{"id":"https://openalex.org/keywords/high-performance-processors","display_name":"high-performance processors","score":0.7039999961853027},{"id":"https://openalex.org/keywords/delay-penalty","display_name":"delay penalty","score":0.4650000035762787}],"concepts":[{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6852933168411255},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6268362998962402},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.565710186958313},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5576608777046204},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4673234522342682},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.45684847235679626},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4449286460876465},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.41224613785743713},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3905630111694336},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37219852209091187},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3572760224342346},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3430732488632202},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24668359756469727},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14335182309150696},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13634222745895386},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12565812468528748},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12078079581260681},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.760383","doi":"https://doi.org/10.1109/4.760383","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.760383","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"id":"https://metadata.un.org/sdg/7","score":0.6600000262260437,"display_name":"Affordable and clean energy"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1483149398","https://openalex.org/W1604713355","https://openalex.org/W1606989584","https://openalex.org/W1830487160","https://openalex.org/W1899064893","https://openalex.org/W2019198721","https://openalex.org/W2122502313","https://openalex.org/W2131894786","https://openalex.org/W2137616964","https://openalex.org/W2138134203","https://openalex.org/W2143805061","https://openalex.org/W2150306869","https://openalex.org/W2169263481","https://openalex.org/W3034699553"],"related_works":["https://openalex.org/W3100944160","https://openalex.org/W1965850601","https://openalex.org/W2978427427","https://openalex.org/W2746929098","https://openalex.org/W4296473373","https://openalex.org/W2542280163","https://openalex.org/W2533122910","https://openalex.org/W1976440785","https://openalex.org/W2059422871","https://openalex.org/W2169337913"],"abstract_inverted_index":{"In":[0],"an":[1],"attempt":[2],"to":[3,20,31],"reduce":[4],"the":[5,41,58,62,78],"pipeline":[6,79],"overhead,":[7,80],"a":[8,21,53,70,88,95],"new":[9],"family":[10,60],"of":[11,23,40,64],"edge-triggered":[12],"flip-flops":[13,18],"has":[14,61],"been":[15],"developed.":[16],"The":[17,37],"belong":[19],"class":[22],"semidynamic":[24],"and":[25,34,52],"dynamic":[26,35],"circuits":[27],"that":[28,92],"can":[29,84],"interface":[30],"both":[32],"static":[33],"circuits.":[36],"main":[38],"features":[39],"basic":[42],"design":[43],"are":[44],"short":[45],"latency,":[46],"small":[47,50,71],"clock":[48,55],"load,":[49],"area,":[51],"single-phase":[54],"scheme.":[56],"Furthermore,":[57],"flip-flop":[59,83],"capability":[63],"easily":[65],"incorporating":[66],"logic":[67,90],"functions":[68],"with":[69],"delay":[72],"penalty.":[73],"This":[74],"feature":[75],"greatly":[76],"reduces":[77],"since":[81],"each":[82],"be":[85],"viewed":[86],"as":[87,94,98],"special":[89],"gate":[91],"serves":[93],"synchronization":[96],"element":[97],"well.":[99]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":7}],"updated_date":"2026-10-12T09:40:04.860316","created_date":"2025-10-10T00:00:00"}