{"id":"https://openalex.org/W2098918036","doi":"https://doi.org/10.1109/4.760374","title":"A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface","display_name":"A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface","publication_year":1999,"publication_date":"1999-05-01","ids":{"openalex":"https://openalex.org/W2098918036","doi":"https://doi.org/10.1109/4.760374","mag":"2098918036"},"language":"en","primary_location":{"id":"doi:10.1109/4.760374","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.760374","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111990986","display_name":"C. Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"C. Kim","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112306635","display_name":"Kye-Hyun Kyung","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"K.-H. Kyung","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111880441","display_name":"W.-P. Jeong","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"W.-P. Jeong","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057549437","display_name":"Jongmin Kim","orcid":"https://orcid.org/0009-0002-0486-5493"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J.-S. Kim","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002590504","display_name":"Byungsoo Moon","orcid":"https://orcid.org/0000-0003-4625-2425"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"B.-S. Moon","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110212600","display_name":"J.-W. Chai","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"J.-W. Chai","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111931705","display_name":"S.-M. Yim","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"S.-M. Yim","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101608850","display_name":"Jin-Yong Choi","orcid":"https://orcid.org/0000-0001-7329-9400"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J.-H. Choi","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020471570","display_name":"Kyuseung Han","orcid":"https://orcid.org/0000-0002-9151-3447"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"K.-H. Han","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013594367","display_name":"C.-J. Park","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"C.-J. Park","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052239802","display_name":"HeeJoung Hwang","orcid":"https://orcid.org/0000-0001-5462-0983"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"H.-S. Hwang","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031498821","display_name":"Ho\u2010Suk Choi","orcid":"https://orcid.org/0000-0001-8156-2934"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"H. Choi","raw_affiliation_strings":["DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design, Memory Division, Samsung Electronics Company Limited, Yongin si, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087127222","display_name":"S.-B. Cho","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S.-B. Cho","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111920876","display_name":"C.L. Portmann","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095722","display_name":"Rambus (United States)","ror":"https://ror.org/00pn5a327","country_code":"US","type":"company","lineage":["https://openalex.org/I4210095722"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. L. Portmann","raw_affiliation_strings":["Rambus, Inc., Mountain View, CA, USA"],"affiliations":[{"raw_affiliation_string":"Rambus, Inc., Mountain View, CA, USA","institution_ids":["https://openalex.org/I4210095722"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078168778","display_name":"S.-I. Cho","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S.-I. Cho","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":15,"corresponding_author_ids":["https://openalex.org/A5111990986"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":2.2994,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.87847392,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"34","issue":"5","first_page":"645","last_page":"652"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8271808624267578},{"id":"https://openalex.org/keywords/megabit","display_name":"Megabit","score":0.6857072114944458},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.5608744621276855},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5499434471130371},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5104328989982605},{"id":"https://openalex.org/keywords/header","display_name":"Header","score":0.46499931812286377},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.45911142230033875},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44096267223358154},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3970787227153778},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34350690245628357},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21751004457473755},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.14462894201278687},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09627512097358704}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8271808624267578},{"id":"https://openalex.org/C185177783","wikidata":"https://www.wikidata.org/wiki/Q3332814","display_name":"Megabit","level":2,"score":0.6857072114944458},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5608744621276855},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5499434471130371},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5104328989982605},{"id":"https://openalex.org/C48105269","wikidata":"https://www.wikidata.org/wiki/Q1141160","display_name":"Header","level":2,"score":0.46499931812286377},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.45911142230033875},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44096267223358154},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3970787227153778},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34350690245628357},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21751004457473755},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14462894201278687},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09627512097358704},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.760374","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.760374","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7300000190734863}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2008242847","https://openalex.org/W2009275112","https://openalex.org/W2085936544","https://openalex.org/W2090523408","https://openalex.org/W2788212596","https://openalex.org/W6748727748"],"related_works":["https://openalex.org/W2155719671","https://openalex.org/W3148726441","https://openalex.org/W2469229085","https://openalex.org/W1983214964","https://openalex.org/W2467408428","https://openalex.org/W2020139811","https://openalex.org/W2542548909","https://openalex.org/W1552191932","https://openalex.org/W2138592424","https://openalex.org/W2082547827"],"abstract_inverted_index":{"A":[0],"2.5-V,":[1],"72-Mbit":[2],"DRAM":[3],"based":[4],"on":[5],"packet":[6],"protocol":[7],"has":[8],"been":[9],"developed":[10],"using":[11,47,82],"(1)":[12],"a":[13,44,48,63,72,83],"rotated":[14],"hierarchical":[15],"I/O":[16,41,85],"architecture":[17,33],"to":[18,23,54,77],"reduce":[19],"power":[20],"noise":[21,68],"and":[22,39,50,70],"minimize":[24],"the":[25,56],"chip-size":[26],"penalty":[27],"associated":[28],"with":[29,35,66],"an":[30],"8-bit":[31],"prefetch":[32],"implemented":[34],"16":[36],"internal":[37],"banks":[38],"144":[40],"lines,":[42],"(2)":[43],"delay-locked-loop":[45],"circuit":[46],"high-speed":[49],"small-swing":[51],"differential":[52],"clock":[53],"achieve":[55],"peak":[57],"bandwidth":[58],"of":[59],"2.0":[60],"GByte/s":[61],"in":[62],"single":[64],"chip":[65],"low":[67],"sensitivity,":[69],"(3)":[71],"flexible":[73],"column":[74],"redundancy":[75,80],"scheme":[76,87],"efficiently":[78],"increase":[79],"coverage":[81],"shifted":[84],"line":[86],"for":[88],"multibank":[89],"architecture.":[90]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}