{"id":"https://openalex.org/W2156566689","doi":"https://doi.org/10.1109/4.563678","title":"Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems","display_name":"Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems","publication_year":1997,"publication_date":"1997-04-01","ids":{"openalex":"https://openalex.org/W2156566689","doi":"https://doi.org/10.1109/4.563678","mag":"2156566689"},"language":"en","primary_location":{"id":"doi:10.1109/4.563678","doi":"https://doi.org/10.1109/4.563678","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.563678","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-3","norway-2"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111649074","display_name":"Fang-shi Lai","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210085935","display_name":"IBM Research - Almaden","ror":"https://ror.org/005w8dd04","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210085935","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fang-Shi Lai","raw_affiliation_strings":["IBM Almaden Research Center, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Almaden Research Center, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210085935"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111568152","display_name":"Wei Hwang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Hwang","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":5.0636,"has_fulltext":false,"cited_by_count":87,"citation_normalized_percentile":{"value":0.95354815,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"32","issue":"4","first_page":"563","last_page":"573"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0017000000225380063,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0015999999595806003,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"pass transistor logic","score":0.7760000228881836},{"id":"https://openalex.org/keywords/standard-cell-library","display_name":"standard cell library","score":0.6330000162124634},{"id":"https://openalex.org/keywords/viterbi-decoder","display_name":"Viterbi decoder","score":0.6710000038146973},{"id":"https://openalex.org/keywords/power-delay-product","display_name":"power-delay product","score":0.777999997138977},{"id":"https://openalex.org/keywords/power-dissipation","display_name":"power dissipation","score":0.593999981880188},{"id":"https://openalex.org/keywords/0-5-mum-cmos","display_name":"0.5 \u03bcm CMOS","score":0.6740000247955322}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.710575520992279},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6599406003952026},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5481196641921997},{"id":"https://openalex.org/C2775946640","wikidata":"https://www.wikidata.org/wiki/Q1735017","display_name":"Cascode","level":4,"score":0.5335313081741333},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5310680866241455},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5269352197647095},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5238502025604248},{"id":"https://openalex.org/C126445297","wikidata":"https://www.wikidata.org/wiki/Q8065380","display_name":"NOR gate","level":4,"score":0.4972679913043976},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.4747788608074188},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.45785200595855713},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.45337292551994324},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45030155777931213},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4185551106929779},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.40531519055366516},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.335979700088501},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.30194586515426636},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30135685205459595},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2752235233783722},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2546970248222351},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21847733855247498},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.08281940221786499},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.563678","doi":"https://doi.org/10.1109/4.563678","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.563678","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-3","norway-2"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"display_name":"Affordable and clean energy","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/7"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W276995","https://openalex.org/W1495414726","https://openalex.org/W1537573727","https://openalex.org/W2000260960","https://openalex.org/W2027852725","https://openalex.org/W2068355008","https://openalex.org/W2100280798","https://openalex.org/W2121820643","https://openalex.org/W2126218897","https://openalex.org/W2135955108","https://openalex.org/W2140958423","https://openalex.org/W2150090234","https://openalex.org/W2565051160","https://openalex.org/W4205908247","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2017528947","https://openalex.org/W1553855433","https://openalex.org/W1593362825","https://openalex.org/W1529529399","https://openalex.org/W2082591327","https://openalex.org/W2155174752","https://openalex.org/W2619968078","https://openalex.org/W3046672745","https://openalex.org/W1979361505"],"abstract_inverted_index":{"In":[0,202],"this":[1],"paper,":[2],"a":[3,26,58,173],"new":[4,59],"high-speed":[5],"circuit":[6,21,121,160,208],"technique":[7,22,161],"called":[8],"differential":[9],"cascode":[10],"voltage":[11],"switch":[12],"with":[13,70,117,145,178,204],"pass-gate":[14,27,92,120],"(DCVSPG)":[15],"logic":[16,28,36,93,125,129,135],"tree":[17,29,37,94],"is":[18,23,111,148,162,169,172],"presented.":[19,138],"The":[20,79,97,114,164],"designed":[24],"using":[25,157],"in":[30,38],"DCVSPG":[31,56,81,109,144,159,218],"instead":[32],"of":[33,61,90,104,108,187],"the":[34,39,45,51,55,84,91,105,143,150,158,167,198,210,216,220],"nMOS":[35],"conventional":[40],"DCVS":[41],"circuit,":[42,63],"which":[43],"eliminates":[44],"floating":[46,52],"node":[47,53],"problem.":[48],"By":[49],"eliminating":[50],"problem,":[54],"becomes":[57],"type":[60],"ratioless":[62],"and":[64,74,88,131,184],"it":[65],"also":[66,112,149,212],"provides":[67],"superior":[68,221],"performance":[69,115],"less":[71],"power":[72],"dissipation":[73],"better":[75],"silicon":[76],"area":[77],"tradeoff.":[78],"basic":[80],"design":[82,156,168],"technique,":[83],"methodology":[85],"for":[86],"optimization,":[87],"synthesis":[89],"are":[95,137],"described.":[96],"standard":[98],"cell":[99],"library":[100],"development":[101],"taking":[102],"advantage":[103],"dual-rail":[106],"outputs":[107],"gates":[110],"discussed.":[113],"comparisons":[116],"other":[118,205],"existing":[119,206],"techniques":[122],"[complimentary":[123],"pass-transistor":[124,128,134],"(CPL),":[126],"double":[127],"(DPL),":[130],"swing":[132],"restored":[133],"(SRPL)]":[136],"For":[139],"more":[140],"robust":[141],"design,":[142],"inverter":[146],"buffers":[147],"best":[151],"choice.":[152],"A":[153],"Viterbi":[154],"macro":[155,190],"demonstrated.":[163],"process":[165,200],"that":[166,215],"based":[170],"upon":[171],"0.5-/spl":[174],"mu/m":[175,180],"CMOS":[176],"technology":[177],"0.25-/spl":[179],"effective":[181],"channel":[182],"length":[183],"five":[185],"layers":[186],"metal.":[188],"This":[189],"can":[191],"run":[192],"up":[193],"to":[194],"500":[195],"MHz":[196],"at":[197],"nominal":[199],"condition.":[201],"comparison":[203],"dynamic":[207,217],"techniques,":[209],"results":[211],"clearly":[213],"show":[214],"has":[219],"power-delay":[222],"performance.":[223]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":3}],"updated_date":"2026-09-22T06:50:58.402377","created_date":"2025-10-10T00:00:00"}