{"id":"https://openalex.org/W2150628095","doi":"https://doi.org/10.1109/4.52180","title":"Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM","display_name":"Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM","publication_year":1990,"publication_date":"1990-04-01","ids":{"openalex":"https://openalex.org/W2150628095","doi":"https://doi.org/10.1109/4.52180","mag":"2150628095"},"language":"en","primary_location":{"id":"doi:10.1109/4.52180","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.52180","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090795865","display_name":"Hiroshi Miyamoto","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"H. Miyamoto","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009203864","display_name":"T. Yamagata","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Yamagata","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013047082","display_name":"S. Mori","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Mori","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017115331","display_name":"T. Aono","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Aono","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006477564","display_name":"I. Ogoh","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Ogoh","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011393565","display_name":"M. Yamada","orcid":"https://orcid.org/0000-0002-9623-9926"},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Yamada","raw_affiliation_strings":["LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Research and Development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5090795865"],"corresponding_institution_ids":["https://openalex.org/I4210133125"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.22691528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"2","first_page":"525","last_page":"530"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8025238513946533},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5658074617385864},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5252330303192139},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5174177885055542},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4996962547302246},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.4823436439037323},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4770228862762451},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4544057250022888},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.43260008096694946},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41034063696861267},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3323267102241516},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2974994480609894},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21870052814483643}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8025238513946533},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5658074617385864},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5252330303192139},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5174177885055542},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4996962547302246},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.4823436439037323},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4770228862762451},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4544057250022888},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.43260008096694946},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41034063696861267},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3323267102241516},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2974994480609894},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21870052814483643},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.52180","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.52180","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1514902900","https://openalex.org/W1833274615","https://openalex.org/W1976282273","https://openalex.org/W1985821426","https://openalex.org/W1989393230","https://openalex.org/W2001151671","https://openalex.org/W2044724053","https://openalex.org/W2066733867","https://openalex.org/W2093888116","https://openalex.org/W2107752016","https://openalex.org/W2132729131","https://openalex.org/W2138809713","https://openalex.org/W2146787620","https://openalex.org/W2153480149","https://openalex.org/W2170651760","https://openalex.org/W2428143052","https://openalex.org/W3142787616","https://openalex.org/W6635313626"],"related_works":["https://openalex.org/W2806295079","https://openalex.org/W3100668214","https://openalex.org/W2788884286","https://openalex.org/W2134643927","https://openalex.org/W2004034743","https://openalex.org/W159155456","https://openalex.org/W2099115487","https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2502451555"],"abstract_inverted_index":{"Improved":[0],"circuits":[1],"for":[2],"a":[3,29,32,110,119,123,135,145,149,158,164],"4-Mb":[4],"CMOS":[5,115],"DRAM":[6],"are":[7,142],"described.":[8],"In":[9],"one":[10],"of":[11,28,40,82,126,148],"them,":[12],"called":[13],"the":[14,20,26,37,41,44,59,75,79,83,100,104],"effective":[15],"one-shot":[16,51],"gate":[17,27],"address":[18,22,61],"buffer,":[19],"input":[21,38,80,88],"is":[23,46,93,155],"provided":[24],"to":[25],"transistor,":[30],"and":[31,43,64,102,118,134,163],"gating":[33],"transistor":[34,45],"located":[35],"between":[36],"node":[39],"buffer":[42,84],"controlled":[47],"by":[48],"an":[49],"equivalent":[50],"pulse":[52],"with":[53,86,122],"sufficient":[54],"high":[55],"level.":[56],"This":[57],"reduces":[58],"row":[60],"hold":[62],"time":[63,133],"also":[65],"RAS-bar":[66,131],"access":[67,132],"time.":[68],"A":[69,129],"standby":[70,76],"current":[71,77,138],"limitation":[72],"circuit":[73],"eliminates":[74],"at":[78,139],"stage":[81],"even":[85],"TTL-level":[87],"voltage.":[89],"Test-mode":[90],"hidden":[91],"refresh":[92],"achieved":[94,143],"without":[95],"test-mode":[96],"resetting,":[97],"which":[98],"enhances":[99],"testability":[101],"relaxes":[103],"test":[105],"sequence.":[106],"The":[107,153],"RAM":[108,154],"employs":[109],"0.8-":[111],"mu":[112],"m":[113],"twin-well":[114],"process":[116],"technology":[117],"stacked":[120],"capacitor":[121],"storage":[124],"capacitance":[125],"35":[127],"fF.":[128],"58-ns":[130],"65-mA":[136],"active":[137],"160-ns":[140],"cycle":[141],"in":[144,157],"die":[146],"size":[147],"6.84":[150],"mm*14.95":[151],"mm.":[152],"housed":[156],"350-mil":[159],"small-outline":[160],"J-leaded":[161],"package":[162],"400-mil":[165],"zig-zag":[166],"in-line":[167],"package.<":[168],"<ETX":[169],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[170],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[171]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}