{"id":"https://openalex.org/W4382052365","doi":"https://doi.org/10.1109/3dic57175.2023.10154953","title":"Chiplet Set For Artificial Intelligence","display_name":"Chiplet Set For Artificial Intelligence","publication_year":2023,"publication_date":"2023-05-10","ids":{"openalex":"https://openalex.org/W4382052365","doi":"https://doi.org/10.1109/3dic57175.2023.10154953"},"language":"en","primary_location":{"id":"doi:10.1109/3dic57175.2023.10154953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic57175.2023.10154953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112945937","display_name":"Joshua A. Stevens","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Joshua A. Stevens","raw_affiliation_strings":["North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047060950","display_name":"Tse-Han Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tse-Han Pan","raw_affiliation_strings":["North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048806501","display_name":"Prasanth Prabu Ravichandiran","orcid":null},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prasanth Prabu Ravichandiran","raw_affiliation_strings":["North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074605796","display_name":"Paul D. Franzon","orcid":"https://orcid.org/0000-0002-6048-5770"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul D. Franzon","raw_affiliation_strings":["North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA"],"affiliations":[{"raw_affiliation_string":"North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA","institution_ids":["https://openalex.org/I137902535"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA","institution_ids":["https://openalex.org/I137902535"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5112945937"],"corresponding_institution_ids":["https://openalex.org/I137902535"],"apc_list":null,"apc_paid":null,"fwci":0.5349,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64124237,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7813614010810852},{"id":"https://openalex.org/keywords/interposer","display_name":"Interposer","score":0.7120073437690735},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.626322865486145},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5133256316184998},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46833276748657227},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46344614028930664},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4192016124725342},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.41555118560791016},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.29571670293807983},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22950148582458496},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1284472942352295}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7813614010810852},{"id":"https://openalex.org/C158802814","wikidata":"https://www.wikidata.org/wiki/Q6056418","display_name":"Interposer","level":4,"score":0.7120073437690735},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.626322865486145},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5133256316184998},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46833276748657227},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46344614028930664},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4192016124725342},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41555118560791016},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.29571670293807983},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22950148582458496},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1284472942352295},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C100460472","wikidata":"https://www.wikidata.org/wiki/Q2368605","display_name":"Etching (microfabrication)","level":3,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic57175.2023.10154953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic57175.2023.10154953","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4891473428","display_name":null,"funder_award_id":"N00014-17-1-2991","funder_id":"https://openalex.org/F4320309327","funder_display_name":"Google"}],"funders":[{"id":"https://openalex.org/F4320308258","display_name":"Qualcomm","ror":"https://ror.org/002zrf773"},{"id":"https://openalex.org/F4320309327","display_name":"Google","ror":"https://ror.org/00njsd438"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W2182927495","https://openalex.org/W2415037989","https://openalex.org/W2620616258","https://openalex.org/W2940722902","https://openalex.org/W2945577986","https://openalex.org/W2954201230","https://openalex.org/W2983878317","https://openalex.org/W3008954557","https://openalex.org/W3016212306","https://openalex.org/W3016874508","https://openalex.org/W3084147765","https://openalex.org/W3108101844","https://openalex.org/W3188178661","https://openalex.org/W4210588783","https://openalex.org/W4296209134","https://openalex.org/W4315489358","https://openalex.org/W4360605745","https://openalex.org/W6686247772","https://openalex.org/W6738779938","https://openalex.org/W6851045374","https://openalex.org/W7066278933"],"related_works":["https://openalex.org/W1998013902","https://openalex.org/W2550108858","https://openalex.org/W1781968824","https://openalex.org/W4247993032","https://openalex.org/W3145476088","https://openalex.org/W2117274229","https://openalex.org/W1963867998","https://openalex.org/W3002622661","https://openalex.org/W2058198174","https://openalex.org/W2125503095"],"abstract_inverted_index":{"The":[0,84,121,130,206],"design":[1,40,64,71],"reuse":[2],"strategy":[3],"has":[4,152],"significantly":[5],"shortened":[6],"the":[7,24,39,52,56,148,192,204],"time":[8],"required":[9],"to":[10,55,202],"create":[11],"complex":[12],"System":[13],"on":[14,139,187],"Chips":[15],"(SoCs).":[16],"However,":[17],"when":[18],"introducing":[19],"new":[20],"intellectual":[21],"properties":[22],"(IPs),":[23],"monolithic":[25],"SoC":[26],"methodology":[27],"requires":[28],"a":[29,62,73,118],"re-run":[30],"of":[31,170],"system-level":[32],"validation":[33,158],"steps,":[34],"incurring":[35],"significant":[36],"costs.":[37],"Partitioning":[38],"into":[41],"chiplets":[42,166],"over":[43],"an":[44,89,107,135,160,182],"interposer":[45,162],"would":[46],"mitigate":[47],"these":[48],"issues":[49],"by":[50],"consigning":[51],"IP":[53,157,180],"updates":[54],"individual":[57],"chiplet.":[58],"This":[59,70,150,184],"paper":[60,185],"presents":[61],"chipletized":[63],"used":[65],"for":[66,101,114,142,146],"Artificial":[67],"Intelligence":[68],"(AI).":[69],"details":[72],"scalable":[74],"AI":[75,85,124],"chiplet":[76,86],"set,":[77],"along":[78],"with":[79,159],"Central":[80],"Processing":[81],"Units":[82],"(CPUs).":[83],"set":[87],"includes":[88],"Long":[90],"Short":[91],"Term":[92],"Memory":[93],"(LSTM)":[94],"Application":[95],"Specific":[96],"Instruction":[97],"Set":[98],"Processor":[99],"(ASIP)":[100],"accelerating":[102,115],"inference":[103,116],"and":[104,106,126,132,144,175],"training":[105],"Sparse":[108],"Convolution":[109],"Neural":[110],"Network":[111,138],"(SCNN)":[112],"ASIP":[113],"through":[117,167,181],"zero-skipping":[119],"technique.":[120],"CPUs":[122,133],"control":[123],"accelerators":[125,131],"handle":[127],"general":[128],"tasks.":[129],"have":[134],"AXI":[136],"crossbar":[137],"Chip":[140],"(NoC)":[141],"memory":[143],"one":[145],"controlling":[147],"accelerators.":[149],"project":[151],"two":[153],"phases:":[154],"phase":[155,176,188],"one,":[156,189],"emulated":[161],"(No":[163],"interposer,":[164],"connect":[165],"back":[168],"end":[169],"line":[171],"(BEOL)":[172],"metal":[173],"layers),":[174],"two,":[177],"connecting":[178],"validated":[179],"interposer.":[183],"focuses":[186],"which":[190],"uses":[191],"United":[193],"Semiconductor":[194],"Japan":[195],"Co.":[196],"(USJC)":[197],"55":[198],"nm":[199],"LP":[200],"process":[201],"fabricate":[203],"design.":[205],"chiplets'":[207],"clock":[208],"frequencies":[209],"range":[210],"from":[211],"200":[212],"-":[213],"400":[214],"MHz.":[215]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}