{"id":"https://openalex.org/W4245867426","doi":"https://doi.org/10.1109/3dic.2013.6702372","title":"Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination","display_name":"Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W4245867426","doi":"https://doi.org/10.1109/3dic.2013.6702372"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2013.6702372","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702372","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037920478","display_name":"Jason Chew","orcid":null},"institutions":[{"id":"https://openalex.org/I4210102879","display_name":"Applied Materials (Singapore)","ror":"https://ror.org/01c4r0z03","country_code":"SG","type":"company","lineage":["https://openalex.org/I193427800","https://openalex.org/I4210102879"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Jason Chew","raw_affiliation_strings":["Applied Materials, Singapore"],"affiliations":[{"raw_affiliation_string":"Applied Materials, Singapore","institution_ids":["https://openalex.org/I4210102879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075751178","display_name":"Uday Mahajan","orcid":"https://orcid.org/0009-0008-6495-1266"},"institutions":[{"id":"https://openalex.org/I4210102879","display_name":"Applied Materials (Singapore)","ror":"https://ror.org/01c4r0z03","country_code":"SG","type":"company","lineage":["https://openalex.org/I193427800","https://openalex.org/I4210102879"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Uday Mahajan","raw_affiliation_strings":["Applied Materials, 10 Science Park Road, Singapore 117684"],"affiliations":[{"raw_affiliation_string":"Applied Materials, 10 Science Park Road, Singapore 117684","institution_ids":["https://openalex.org/I4210102879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110601592","display_name":"Rajeev Bajaj","orcid":null},"institutions":[{"id":"https://openalex.org/I193427800","display_name":"Applied Materials (United States)","ror":"https://ror.org/04h1q4c89","country_code":"US","type":"company","lineage":["https://openalex.org/I193427800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajeev Bajaj","raw_affiliation_strings":["Applied Materials, Santa Clara"],"affiliations":[{"raw_affiliation_string":"Applied Materials, Santa Clara","institution_ids":["https://openalex.org/I193427800"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084511616","display_name":"Iad Mirshad","orcid":null},"institutions":[{"id":"https://openalex.org/I4210162143","display_name":"QED Technologies (United States)","ror":"https://ror.org/04wz8fg60","country_code":"US","type":"company","lineage":["https://openalex.org/I4210162143"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Iad Mirshad","raw_affiliation_strings":["Qcept Technologies, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"Qcept Technologies, Atlanta, GA","institution_ids":["https://openalex.org/I4210162143"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091032119","display_name":"R.W. Newcomb","orcid":null},"institutions":[{"id":"https://openalex.org/I4210162143","display_name":"QED Technologies (United States)","ror":"https://ror.org/04wz8fg60","country_code":"US","type":"company","lineage":["https://openalex.org/I4210162143"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Newcomb","raw_affiliation_strings":["Qcept Technologies, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"Qcept Technologies, Atlanta, GA","institution_ids":["https://openalex.org/I4210162143"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5037920478"],"corresponding_institution_ids":["https://openalex.org/I4210102879"],"apc_list":null,"apc_paid":null,"fwci":0.2364,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66235504,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.7559068202972412},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.5903865098953247},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.571800708770752},{"id":"https://openalex.org/keywords/process-integration","display_name":"Process integration","score":0.5295100212097168},{"id":"https://openalex.org/keywords/wafer-scale-integration","display_name":"Wafer-scale integration","score":0.518038809299469},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5060262084007263},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.48923206329345703},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4745691120624542},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.4734511077404022},{"id":"https://openalex.org/keywords/integrated-circuit-packaging","display_name":"Integrated circuit packaging","score":0.4546350836753845},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.42928755283355713},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4279947876930237},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.426535964012146},{"id":"https://openalex.org/keywords/wafer-level-packaging","display_name":"Wafer-level packaging","score":0.4133955240249634},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.406583309173584},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.39078301191329956},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.36045411229133606},{"id":"https://openalex.org/keywords/process-engineering","display_name":"Process engineering","score":0.20154604315757751},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17976146936416626}],"concepts":[{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.7559068202972412},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5903865098953247},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.571800708770752},{"id":"https://openalex.org/C54725748","wikidata":"https://www.wikidata.org/wiki/Q7247277","display_name":"Process integration","level":2,"score":0.5295100212097168},{"id":"https://openalex.org/C2778638305","wikidata":"https://www.wikidata.org/wiki/Q7406100","display_name":"Wafer-scale integration","level":3,"score":0.518038809299469},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5060262084007263},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.48923206329345703},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4745691120624542},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.4734511077404022},{"id":"https://openalex.org/C186260285","wikidata":"https://www.wikidata.org/wiki/Q759494","display_name":"Integrated circuit packaging","level":3,"score":0.4546350836753845},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.42928755283355713},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4279947876930237},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.426535964012146},{"id":"https://openalex.org/C2780288131","wikidata":"https://www.wikidata.org/wiki/Q4017648","display_name":"Wafer-level packaging","level":3,"score":0.4133955240249634},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.406583309173584},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.39078301191329956},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.36045411229133606},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.20154604315757751},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17976146936416626},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic.2013.6702372","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702372","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1989035467","https://openalex.org/W2109622694","https://openalex.org/W6647637343"],"related_works":["https://openalex.org/W2027159884","https://openalex.org/W1990828594","https://openalex.org/W2089377260","https://openalex.org/W2156194080","https://openalex.org/W2046139226","https://openalex.org/W2513353273","https://openalex.org/W2549021975","https://openalex.org/W2333804548","https://openalex.org/W1968957853","https://openalex.org/W2088052449"],"abstract_inverted_index":{"Through":[0],"Silicon":[1],"Vias":[2],"(TSV)":[3],"is":[4,31],"a":[5,21],"key":[6,35],"technology":[7],"for":[8],"advanced":[9],"3DIC":[10],"packaging,":[11],"enabling":[12],"improved":[13],"device":[14],"performance,":[15],"integration":[16,39],"of":[17,33],"multiple":[18],"functions":[19],"in":[20,37],"single":[22],"package":[23],"and":[24],"form":[25],"factor":[26],"reduction.":[27],"TSV":[28],"reveal":[29],"CMP":[30],"one":[32],"the":[34],"processes":[36],"this":[38],"scheme":[40],"[1].":[41]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}