{"id":"https://openalex.org/W1974550490","doi":"https://doi.org/10.1109/3dic.2013.6702347","title":"A high-performance multiported L2 memory IP for scalable three-dimensional integration","display_name":"A high-performance multiported L2 memory IP for scalable three-dimensional integration","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W1974550490","doi":"https://doi.org/10.1109/3dic.2013.6702347","mag":"1974550490"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2013.6702347","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054896676","display_name":"Erfan Azarkhish","orcid":"https://orcid.org/0000-0003-4934-0332"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Erfan Azarkhish","raw_affiliation_strings":["DEI, University of Bologna, Bologna, Italy","Micrel Lab., Univ. of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Micrel Lab., Univ. of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046255006","display_name":"Igor Loi","orcid":"https://orcid.org/0000-0003-3852-4662"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Igor Loi","raw_affiliation_strings":["DEI, University of Bologna, Bologna, Italy","Micrel Lab., Univ. of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"Micrel Lab., Univ. of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEI, University of Bologna, Bologna, Italy","DEI, University of Bologna,Bologna,Italy"],"affiliations":[{"raw_affiliation_string":"DEI, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]},{"raw_affiliation_string":"DEI, University of Bologna,Bologna,Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5054896676"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":0.36207187,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.64034467,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"37","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7758122086524963},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6388829946517944},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5733774900436401},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5525436997413635},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5124407410621643},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5081231594085693},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.507070779800415},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4936908185482025},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.47289028763771057},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.43688786029815674},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4253147840499878},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4213825464248657},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4158391058444977},{"id":"https://openalex.org/keywords/conventional-memory","display_name":"Conventional memory","score":0.41210705041885376},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3689786195755005},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.36506134271621704},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.32964015007019043},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.24218830466270447},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.107514888048172}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7758122086524963},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6388829946517944},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5733774900436401},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5525436997413635},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5124407410621643},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5081231594085693},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.507070779800415},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4936908185482025},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.47289028763771057},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.43688786029815674},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4253147840499878},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4213825464248657},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4158391058444977},{"id":"https://openalex.org/C53838383","wikidata":"https://www.wikidata.org/wiki/Q541148","display_name":"Conventional memory","level":5,"score":0.41210705041885376},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3689786195755005},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.36506134271621704},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.32964015007019043},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.24218830466270447},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.107514888048172},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/3dic.2013.6702347","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2013.6702347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/388156","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/388156","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.699999988079071,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1974135132","https://openalex.org/W1990416701","https://openalex.org/W1991932360","https://openalex.org/W1993989849","https://openalex.org/W2010802738","https://openalex.org/W2023264348","https://openalex.org/W2035720033","https://openalex.org/W2047043979","https://openalex.org/W2061587924","https://openalex.org/W2062173292","https://openalex.org/W2071208935","https://openalex.org/W2086481541","https://openalex.org/W2093291516","https://openalex.org/W2096169320","https://openalex.org/W2098872535","https://openalex.org/W2100516830","https://openalex.org/W2104283712","https://openalex.org/W2115246441","https://openalex.org/W2122636510","https://openalex.org/W2125213532","https://openalex.org/W2126339718","https://openalex.org/W2131413854","https://openalex.org/W2131428184","https://openalex.org/W2132321891","https://openalex.org/W2136011486","https://openalex.org/W2139730616","https://openalex.org/W2146093007","https://openalex.org/W2147657366","https://openalex.org/W2153215457","https://openalex.org/W2156519590","https://openalex.org/W2159217072","https://openalex.org/W2159218826","https://openalex.org/W2166695060","https://openalex.org/W3139689176","https://openalex.org/W3140078554","https://openalex.org/W3140430354","https://openalex.org/W3143819208","https://openalex.org/W3144500201","https://openalex.org/W4231938743","https://openalex.org/W4236212678","https://openalex.org/W4239080746","https://openalex.org/W4253600620","https://openalex.org/W6682540009"],"related_works":["https://openalex.org/W3180803030","https://openalex.org/W1974211070","https://openalex.org/W2078720616","https://openalex.org/W2168550483","https://openalex.org/W2047684617","https://openalex.org/W2145484885","https://openalex.org/W1575240748","https://openalex.org/W1975698617","https://openalex.org/W2378551620","https://openalex.org/W2151401558"],"abstract_inverted_index":{"L2":[0,40],"memory,":[1],"serving":[2],"multiple":[3,86,93],"clusters":[4],"of":[5,37,85,113,126,174],"tightly":[6],"coupled":[7],"processors,":[8],"is":[9],"well-suited":[10],"for":[11],"3D":[12,70],"integration,":[13],"given":[14],"its":[15,54,103,154],"large":[16],"required":[17],"size":[18],"and":[19,23,57,96],"tolerance":[20],"to":[21,48,102,115,160,164],"latency":[22,79],"variations":[24],"in":[25,121,141],"memory":[26,41,60,72,87,134,149,171],"access":[27,61,73,151],"time.":[28],"In":[29],"this":[30],"paper,":[31],"we":[32],"focus":[33],"on":[34,77],"the":[35],"design":[36],"a":[38,49,68,116,170],"synthesizable":[39],"IP":[42],"component,":[43],"which":[44,82],"can":[45,119,136,157],"be":[46],"attached":[47],"cluster-based":[50],"multi-core":[51,117],"platform":[52],"through":[53],"NoC":[55,118],"ports,":[56],"offer":[58],"high-bandwidth":[59],"with":[62,89,169],"low":[63,78],"average":[64,123],"latency.":[65],"We":[66],"propose":[67],"scalable":[69],"nonuniform":[71],"(NUMA)":[74],"architecture,":[75],"based":[76],"logarithmic":[80],"interconnects,":[81],"allows":[83],"stacking":[84],"layers":[88,166],"identical":[90],"dies,":[91],"supports":[92],"outstanding":[94],"transactions,":[95],"achieves":[97],"high":[98],"clock":[99],"frequencies":[100],"due":[101],"highly":[104],"pipelined":[105],"nature.":[106],"Benchmark":[107],"simulation":[108],"results":[109,130],"demonstrate":[110],"that":[111,132],"addition":[112],"3D-NUMA":[114,133],"result":[120],"an":[122],"performance":[124],"boost":[125],"34%.":[127],"Physical":[128],"synthesis":[129],"show":[131],"system":[135],"operate":[137,158],"at":[138],"500":[139],"MHz":[140],"STMicroelec-tronics":[142],"CMOS-28nm":[143],"Low":[144],"Power":[145],"Technology":[146],"(bounded":[147],"by":[148],"cut":[150],"time,":[152],"while":[153],"logic":[155],"components":[156],"up":[159,163],"1":[161],"GHz),":[162],"8":[165],"(4":[167],"MB)":[168],"density":[172],"loss":[173],"only":[175],"16%.":[176]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-02-09T09:26:11.010843","created_date":"2025-10-10T00:00:00"}