{"id":"https://openalex.org/W1987191605","doi":"https://doi.org/10.1109/3dic.2012.6263029","title":"Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration","display_name":"Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W1987191605","doi":"https://doi.org/10.1109/3dic.2012.6263029","mag":"1987191605"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2012.6263029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2012.6263029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113650812","display_name":"Omar Hammami","orcid":null},"institutions":[{"id":"https://openalex.org/I201181511","display_name":"\u00c9cole Nationale Sup\u00e9rieure de Techniques Avanc\u00e9es","ror":"https://ror.org/0309cs235","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"O. Hammami","raw_affiliation_strings":["ENSTA ParisTech, Paris, France","ENSTA ParisTech 32, Bvd Victor 75739 Paris France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA ParisTech, Paris, France","institution_ids":["https://openalex.org/I201181511"]},{"raw_affiliation_string":"ENSTA ParisTech 32, Bvd Victor 75739 Paris France","institution_ids":["https://openalex.org/I201181511"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013656767","display_name":"Abir M'zah","orcid":null},"institutions":[{"id":"https://openalex.org/I201181511","display_name":"\u00c9cole Nationale Sup\u00e9rieure de Techniques Avanc\u00e9es","ror":"https://ror.org/0309cs235","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A. M'zah","raw_affiliation_strings":["ENSTA ParisTech, Paris, France","ENSTA ParisTech 32, Bvd Victor 75739 Paris France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA ParisTech, Paris, France","institution_ids":["https://openalex.org/I201181511"]},{"raw_affiliation_string":"ENSTA ParisTech 32, Bvd Victor 75739 Paris France","institution_ids":["https://openalex.org/I201181511"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076684291","display_name":"Khawla Hamwi","orcid":null},"institutions":[{"id":"https://openalex.org/I201181511","display_name":"\u00c9cole Nationale Sup\u00e9rieure de Techniques Avanc\u00e9es","ror":"https://ror.org/0309cs235","country_code":"FR","type":"education","lineage":["https://openalex.org/I201181511","https://openalex.org/I4210145102"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"K. Hamwi","raw_affiliation_strings":["ENSTA ParisTech, Paris, France","ENSTA ParisTech 32, Bvd Victor 75739 Paris France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ENSTA ParisTech, Paris, France","institution_ids":["https://openalex.org/I201181511"]},{"raw_affiliation_string":"ENSTA ParisTech 32, Bvd Victor 75739 Paris France","institution_ids":["https://openalex.org/I201181511"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201181511"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"32","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6604230999946594},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6536992192268372},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6517722606658936},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6480594873428345},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6325920820236206},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5987439155578613},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5627965331077576},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5361599326133728},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.503264844417572},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4859551191329956},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4699038863182068},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4498790502548218},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3331919014453888},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.30823415517807007},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2618159353733063},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2047824263572693},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13583603501319885},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1357613503932953}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6604230999946594},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6536992192268372},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6517722606658936},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6480594873428345},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6325920820236206},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5987439155578613},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5627965331077576},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5361599326133728},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.503264844417572},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4859551191329956},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4699038863182068},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4498790502548218},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3331919014453888},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.30823415517807007},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2618159353733063},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2047824263572693},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13583603501319885},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1357613503932953},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic.2012.6263029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2012.6263029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2027712195","https://openalex.org/W2054461765","https://openalex.org/W2079223887","https://openalex.org/W2109188922","https://openalex.org/W2157427983","https://openalex.org/W3145452004","https://openalex.org/W6670620217"],"related_works":["https://openalex.org/W2102097772","https://openalex.org/W2102965264","https://openalex.org/W2129188682","https://openalex.org/W3207646743","https://openalex.org/W2119428232","https://openalex.org/W3148440458","https://openalex.org/W2338273177","https://openalex.org/W2115761834","https://openalex.org/W2806920922","https://openalex.org/W2040486315"],"abstract_inverted_index":{"3D":[0,47,57],"Conception":[1],"is":[2,14],"an":[3],"efficient":[4],"solution":[5],"to":[6,44,55,69],"deal":[7],"with":[8,59],"the":[9,16,28,56,64,67,70,75],"global":[10],"wiring":[11],"delay":[12,18],"which":[13],"overcoming":[15],"gates":[17],"in":[19,25],"nanometres":[20],"CMOS":[21],"technology.":[22,41],"We":[23],"present":[24,50],"this":[26],"paper,":[27],"implementation":[29,58],"of":[30,66],"a":[31,46],"butterfly":[32],"NOC":[33],"based":[34],"64":[35],"PE":[36],"multicore":[37],"using":[38],"3D-IC":[39],"Tezzaron":[40],"In":[42],"order":[43],"design":[45],"NOC,":[48],"we":[49,62,73],"different":[51],"partionning":[52],"configurations.":[53],"Thanks":[54],"2":[60],"tiers,":[61],"reduced":[63,74],"area":[65],"chip":[68],"half":[71],"and":[72],"long":[76],"interconnect":[77],"delay.":[78]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}