{"id":"https://openalex.org/W2157643673","doi":"https://doi.org/10.1109/3dic.2012.6263022","title":"A novel reconfigurable logic device base on 3D stack technology","display_name":"A novel reconfigurable logic device base on 3D stack technology","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2157643673","doi":"https://doi.org/10.1109/3dic.2012.6263022","mag":"2157643673"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2012.6263022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2012.6263022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051831948","display_name":"Qian Zhao","orcid":"https://orcid.org/0000-0003-0032-1974"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Qian Zhao","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014924383","display_name":"Yusuke Iwai","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yusuke Iwai","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012465812","display_name":"Motoki Amagasaki","orcid":"https://orcid.org/0000-0002-5196-9765"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Motoki Amagasaki","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059705629","display_name":"Masahiro Iida","orcid":"https://orcid.org/0000-0002-9654-2319"},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Iida","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031401749","display_name":"Toshinori Sueyoshi","orcid":null},"institutions":[{"id":"https://openalex.org/I96036126","display_name":"Kumamoto University","ror":"https://ror.org/02cgss904","country_code":"JP","type":"education","lineage":["https://openalex.org/I96036126"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshinori Sueyoshi","raw_affiliation_strings":["Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan","institution_ids":["https://openalex.org/I96036126"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5051831948"],"corresponding_institution_ids":["https://openalex.org/I96036126"],"apc_list":null,"apc_paid":null,"fwci":0.5008,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.71297694,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.8408508896827698},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7061880230903625},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.691043496131897},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6840049624443054},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6642963886260986},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.6351563334465027},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5797190070152283},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5723869204521179},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5237786173820496},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5193432569503784},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49675875902175903},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.48958906531333923},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4795638918876648},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.44369128346443176},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.41330069303512573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40783217549324036},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3557342290878296},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09753087162971497},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06965580582618713}],"concepts":[{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.8408508896827698},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7061880230903625},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.691043496131897},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6840049624443054},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6642963886260986},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.6351563334465027},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5797190070152283},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5723869204521179},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5237786173820496},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5193432569503784},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49675875902175903},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.48958906531333923},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4795638918876648},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.44369128346443176},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.41330069303512573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40783217549324036},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3557342290878296},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09753087162971497},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06965580582618713},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic.2012.6263022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2012.6263022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1971966678","https://openalex.org/W2035847677","https://openalex.org/W2069907884","https://openalex.org/W2102047509","https://openalex.org/W2131055836","https://openalex.org/W2133743520","https://openalex.org/W2139243942","https://openalex.org/W2145036220","https://openalex.org/W6668030643"],"related_works":["https://openalex.org/W2480852620","https://openalex.org/W2135636985","https://openalex.org/W2182398074","https://openalex.org/W2246445978","https://openalex.org/W3023652529","https://openalex.org/W4237841534","https://openalex.org/W2071567894","https://openalex.org/W2038293309","https://openalex.org/W2139569078","https://openalex.org/W2118828191"],"abstract_inverted_index":{"In":[0,46],"recent":[1],"years,":[2],"as":[3],"the":[4,15,18,35,62,83],"VLSI":[5],"process":[6],"scale":[7],"had":[8],"been":[9],"developed":[10],"into":[11],"deep":[12],"sub-micro":[13],"dimension,":[14],"problem":[16],"of":[17,41,67,74,89],"routing":[19,36,54,72,91],"delay":[20,44],"becomes":[21],"critical.":[22],"Especially":[23],"for":[24],"reconfigurable":[25,75],"logic":[26,76],"devices":[27,77],"(RLDs)":[28],"like":[29],"Field":[30],"Programmable":[31],"Gate":[32],"Arrays":[33],"(FPGAs),":[34],"resources":[37],"occupy":[38],"approximately":[39],"90%":[40],"area":[42,97],"and":[43,64],"performance.":[45],"this":[47],"paper,":[48],"we":[49],"propose":[50],"a":[51],"novel":[52,84],"3D":[53,59,90],"architecture":[55,92],"based":[56],"on":[57,61,95],"building":[58],"connections":[60],"input":[63],"output":[65],"pins":[66],"Logic":[68],"Block":[69],"to":[70],"improve":[71],"performance":[73],"(RLDs).":[78],"The":[79],"evaluation":[80],"shows":[81],"that":[82],"RLD":[85],"with":[86],"two":[87],"layers":[88],"reduced":[93],"51.11%":[94],"borad":[96],"than":[98],"conventional":[99],"2D":[100],"4-LUT":[101],"island":[102],"style":[103],"FPGA.":[104]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-03T22:45:19.894376","created_date":"2025-10-10T00:00:00"}
