{"id":"https://openalex.org/W2158520123","doi":"https://doi.org/10.1109/3dic.2009.5306582","title":"Architectural evaluation of 3D stacked RRAM caches","display_name":"Architectural evaluation of 3D stacked RRAM caches","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2158520123","doi":"https://doi.org/10.1109/3dic.2009.5306582","mag":"2158520123"},"language":"en","primary_location":{"id":"doi:10.1109/3dic.2009.5306582","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2009.5306582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on 3D System Integration","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072449537","display_name":"Dean L. Lewis","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dean L. Lewis","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072539515","display_name":"Hsien-Hsin S. Lee","orcid":"https://orcid.org/0000-0002-8926-8243"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hsien-Hsin S. Lee","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072449537"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":8.3741,"has_fulltext":false,"cited_by_count":79,"citation_normalized_percentile":{"value":0.98039481,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11128","display_name":"Transition Metal Oxide Nanomaterials","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2507","display_name":"Polymers and Plastics"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.9629170298576355},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7808321118354797},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7582283616065979},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6380608081817627},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5356575846672058},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.48744943737983704},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.4688858687877655},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.44183269143104553},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.40314388275146484},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36528533697128296},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3520982265472412},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.342262327671051},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2903876304626465},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23984473943710327},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.1767115592956543},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1132696270942688}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.9629170298576355},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7808321118354797},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7582283616065979},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6380608081817627},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5356575846672058},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.48744943737983704},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.4688858687877655},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.44183269143104553},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.40314388275146484},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36528533697128296},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3520982265472412},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.342262327671051},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2903876304626465},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23984473943710327},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.1767115592956543},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1132696270942688},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/3dic.2009.5306582","is_oa":false,"landing_page_url":"https://doi.org/10.1109/3dic.2009.5306582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on 3D System Integration","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.4699999988079071,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1666750238","https://openalex.org/W2000979663","https://openalex.org/W2027895023","https://openalex.org/W2084007230","https://openalex.org/W2099443680","https://openalex.org/W2112181056","https://openalex.org/W2131413854","https://openalex.org/W2162651880","https://openalex.org/W2540524026","https://openalex.org/W3145669514"],"related_works":["https://openalex.org/W2169710001","https://openalex.org/W1977963439","https://openalex.org/W2315140189","https://openalex.org/W1589619473","https://openalex.org/W4385501094","https://openalex.org/W1968537616","https://openalex.org/W2109866011","https://openalex.org/W3140150102","https://openalex.org/W1567000137","https://openalex.org/W2157007809"],"abstract_inverted_index":{"The":[0,48],"first":[1],"memristor,":[2],"originally":[3],"theorized":[4],"by":[5,13,97],"Dr.":[6],"Leon":[7],"Chua":[8],"in":[9,19,28,57],"1971,":[10],"was":[11],"identified":[12],"a":[14,41,54,58,81,98,106,131,139,155,161],"team":[15],"at":[16],"HP":[17],"Labs":[18],"2008.":[20],"This":[21],"new":[22,113],"fundamental":[23],"circuit":[24],"element":[25],"is":[26,56,79,136,146],"unique":[27],"that":[29,93,135],"its":[30],"resistance":[31],"changes":[32],"as":[33],"current":[34],"passes":[35],"through":[36],"it,":[37],"giving":[38],"the":[39,44,91,128,150],"device":[40,55],"memory":[42,73,134,145],"of":[43,52,75,100,130],"past":[45],"system":[46],"state.":[47],"immediately":[49],"obvious":[50],"application":[51],"such":[53],"non-volatile":[59],"memory,":[60],"wherein":[61],"high-":[62],"and":[63,104,111,119,142],"low-resistance":[64],"states":[65],"are":[66],"used":[67],"to":[68,166],"store":[69],"binary":[70],"values.":[71],"A":[72],"array":[74],"memristors":[76,92],"forms":[77],"what":[78],"called":[80],"resistive":[82],"RAM":[83],"or":[84],"RRAM.":[85],"In":[86,124],"this":[87,112],"paper,":[88],"we":[89,126],"survey":[90],"have":[94],"been":[95],"produced":[96],"number":[99],"different":[101],"research":[102],"teams":[103],"present":[105],"point-by-point":[107],"comparison":[108],"between":[109],"DRAM":[110,168],"RRAM,":[114],"based":[115],"on":[116],"both":[117],"existent":[118],"expected":[120],"near-term":[121],"memristor":[122],"devices.":[123],"particular,":[125],"consider":[127],"case":[129],"die-stacked":[132],"3D":[133],"integrated":[137],"onto":[138],"logic":[140],"die":[141],"evaluate":[143],"which":[144],"best":[147],"suited":[148],"for":[149],"job.":[151],"While":[152],"still":[153],"suffering":[154],"few":[156],"shortcomings,":[157],"RRAM":[158],"proves":[159],"itself":[160],"very":[162],"interesting":[163],"design":[164],"alternative":[165],"well-established":[167],"technologies.":[169]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":12}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}