{"id":"https://openalex.org/W2150050611","doi":"https://doi.org/10.1109/.2006.1629419","title":"Avoiding Store Misses to Fully Modified Cache Blocks","display_name":"Avoiding Store Misses to Fully Modified Cache Blocks","publication_year":2006,"publication_date":"2006-05-25","ids":{"openalex":"https://openalex.org/W2150050611","doi":"https://doi.org/10.1109/.2006.1629419","mag":"2150050611"},"language":"en","primary_location":{"id":"doi:10.1109/.2006.1629419","is_oa":false,"landing_page_url":"https://doi.org/10.1109/.2006.1629419","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Performance Computing and Communications Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026367292","display_name":"Shiwen Hu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shiwen Hu","raw_affiliation_strings":["Networking and Computing Systems Group, Freescale Semiconductor, Inc., Austin, TX, USA","Networking & Comput. Syst. Group, Freescale Semicond., Inc., Austin, TX"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Networking and Computing Systems Group, Freescale Semiconductor, Inc., Austin, TX, USA","institution_ids":[]},{"raw_affiliation_string":"Networking & Comput. Syst. Group, Freescale Semicond., Inc., Austin, TX","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068885069","display_name":"Lizy K. John","orcid":"https://orcid.org/0000-0002-8747-5214"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. John","raw_affiliation_strings":["Laboratory for Computer Architecture, University of Texas, Austin, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory for Computer Architecture, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8537,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.74610925,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"289","last_page":"296"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8488526344299316},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7883708477020264},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6640702486038208},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5336022973060608},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5331252217292786},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.44338458776474},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4368603825569153},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4255691170692444},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.41609442234039307},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.4125474989414215},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3248857855796814}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8488526344299316},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7883708477020264},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6640702486038208},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5336022973060608},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5331252217292786},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.44338458776474},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4368603825569153},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4255691170692444},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41609442234039307},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.4125474989414215},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3248857855796814}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/.2006.1629419","is_oa":false,"landing_page_url":"https://doi.org/10.1109/.2006.1629419","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Performance Computing and Communications Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.300.9804","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.300.9804","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://lca.ece.utexas.edu/pubs/shiwen-ipccc06.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5199999809265137,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1983096721","https://openalex.org/W2030532012","https://openalex.org/W2032094184","https://openalex.org/W2100913437","https://openalex.org/W2120230074","https://openalex.org/W2143285027","https://openalex.org/W2152390090","https://openalex.org/W2154346069","https://openalex.org/W2154693467","https://openalex.org/W2171989104","https://openalex.org/W2172055295","https://openalex.org/W2201109483","https://openalex.org/W2799140574","https://openalex.org/W3142147837","https://openalex.org/W4206635466","https://openalex.org/W4237150160","https://openalex.org/W4250613128","https://openalex.org/W4253048710","https://openalex.org/W4253253513","https://openalex.org/W4254976187","https://openalex.org/W4292169167","https://openalex.org/W6682471944","https://openalex.org/W6687686577","https://openalex.org/W6792903772"],"related_works":["https://openalex.org/W2363769136","https://openalex.org/W2133489088","https://openalex.org/W3085471909","https://openalex.org/W2031173804","https://openalex.org/W2114386333","https://openalex.org/W2734782074","https://openalex.org/W2115222420","https://openalex.org/W2126408955","https://openalex.org/W2098406302","https://openalex.org/W2148571123"],"abstract_inverted_index":{"Memory":[0],"bandwidth":[1],"limitation":[2],"is":[3,37],"one":[4],"of":[5,17,59,79,119],"the":[6,53,60,64,96,111],"major":[7],"impediments":[8],"to":[9,24,122,138],"high-performance":[10],"microprocessors.":[11],"This":[12,132],"paper":[13],"investigates":[14],"a":[15,73,92,123],"class":[16],"store":[18,29,97,106],"misses":[19,30,81,121],"that":[20,71],"can":[21,48],"be":[22,49],"eliminated":[23],"reduce":[25],"data":[26,36,66,76,112,126],"traffic.":[27,67,113],"Those":[28],"fetch":[31],"cache":[32,54,80],"blocks":[33,47,104],"whose":[34],"original":[35],"never":[38],"used.":[39],"If":[40],"fully":[41],"overwritten":[42],"by":[43],"subsequent":[44],"stores,":[45],"those":[46],"installed":[50],"directly":[51,102],"in":[52,129],"without":[55],"accessing":[56],"lower":[57],"levels":[58],"memory":[61],"hierarchy,":[62],"eliminating":[63],"corresponding":[65],"Our":[68],"results":[69],"indicate":[70],"for":[72,105],"1":[74],"MB":[75],"cache,":[77,127],"28%":[78],"are":[82],"avoidable":[83],"across":[84],"SPEC":[85],"CPU":[86],"INT":[87],"2000":[88],"benchmarks.":[89],"We":[90],"propose":[91],"simple":[93],"hardware":[94],"mechanism,":[95],"fill":[98],"buffer":[99],"(SFB),":[100],"which":[101],"installs":[103],"misses,":[107],"and":[108],"substantially":[109],"reduces":[110],"A":[114],"16-entry":[115],"SFB":[116],"eliminates":[117],"16%":[118],"overall":[120],"64":[124],"KB":[125],"resulting":[128],"6%":[130],"speedup.":[131],"mechanism":[133],"enables":[134],"other":[135],"bandwidth-hungry":[136],"techniques":[137],"further":[139],"improve":[140],"system":[141],"performance":[142]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
