{"id":"https://openalex.org/W2966758645","doi":"https://doi.org/10.1080/17445760.2019.1649403","title":"Multi-input volistor logic XNOR gates","display_name":"Multi-input volistor logic XNOR gates","publication_year":2019,"publication_date":"2019-07-31","ids":{"openalex":"https://openalex.org/W2966758645","doi":"https://doi.org/10.1080/17445760.2019.1649403","mag":"2966758645"},"language":"en","primary_location":{"id":"doi:10.1080/17445760.2019.1649403","is_oa":false,"landing_page_url":"https://doi.org/10.1080/17445760.2019.1649403","pdf_url":null,"source":{"id":"https://openalex.org/S85375271","display_name":"International Journal of Parallel Emergent and Distributed Systems","issn_l":"1744-5760","issn":["1744-5760","1744-5779"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320547","host_organization_name":"Taylor & Francis","host_organization_lineage":["https://openalex.org/P4310320547"],"host_organization_lineage_names":["Taylor & Francis"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Parallel, Emergent and Distributed Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000601992","display_name":"Muayad J. Aljafar","orcid":"https://orcid.org/0000-0001-7336-4444"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Muayad J. Aljafar","raw_affiliation_strings":["Electrical and Computer Department, Portland State University, Portland, OR, USA"],"raw_orcid":"https://orcid.org/0000-0001-7336-4444","affiliations":[{"raw_affiliation_string":"Electrical and Computer Department, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048693034","display_name":"Marek Perkowski","orcid":"https://orcid.org/0000-0002-0358-1176"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marek A. Perkowski","raw_affiliation_strings":["Electrical and Computer Department, Portland State University, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Department, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060918291","display_name":"John M. Acken","orcid":"https://orcid.org/0000-0003-0995-2334"},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John M. Acken","raw_affiliation_strings":["Electrical and Computer Department, Portland State University, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Department, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5000601992"],"corresponding_institution_ids":["https://openalex.org/I126345244"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07159038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"35","issue":"4","first_page":"423","last_page":"432"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.9979997873306274},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7363004684448242},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5624492168426514},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5257871150970459},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.46701934933662415},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.4242950677871704},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42027193307876587},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40109431743621826},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.3524235486984253},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3245108723640442},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2539885640144348},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2421998679637909},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.19374823570251465},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.1894265115261078},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.16022497415542603}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.9979997873306274},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7363004684448242},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5624492168426514},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5257871150970459},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.46701934933662415},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.4242950677871704},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42027193307876587},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40109431743621826},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.3524235486984253},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3245108723640442},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2539885640144348},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2421998679637909},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.19374823570251465},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.1894265115261078},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.16022497415542603}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1080/17445760.2019.1649403","is_oa":false,"landing_page_url":"https://doi.org/10.1080/17445760.2019.1649403","pdf_url":null,"source":{"id":"https://openalex.org/S85375271","display_name":"International Journal of Parallel Emergent and Distributed Systems","issn_l":"1744-5760","issn":["1744-5760","1744-5779"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320547","host_organization_name":"Taylor & Francis","host_organization_lineage":["https://openalex.org/P4310320547"],"host_organization_lineage_names":["Taylor & Francis"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Parallel, Emergent and Distributed Systems","raw_type":"journal-article"},{"id":"pmh:oai:pdxscholar.library.pdx.edu:ece_fac-1499","is_oa":false,"landing_page_url":"https://pdxscholar.library.pdx.edu/ece_fac/496","pdf_url":null,"source":{"id":"https://openalex.org/S4377196300","display_name":"PDXScholar  (Portland State University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126345244","host_organization_name":"Portland State University","host_organization_lineage":["https://openalex.org/I126345244"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering Faculty Publications and Presentations","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1538644307","https://openalex.org/W1544945356","https://openalex.org/W1985868795","https://openalex.org/W2004782555","https://openalex.org/W2027895023","https://openalex.org/W2029505831","https://openalex.org/W2052793545","https://openalex.org/W2062960066","https://openalex.org/W2168473504","https://openalex.org/W2195265150","https://openalex.org/W2323986115","https://openalex.org/W2509369410","https://openalex.org/W2521878335","https://openalex.org/W2549589239","https://openalex.org/W2743575791","https://openalex.org/W2760452677","https://openalex.org/W2778155126"],"related_works":["https://openalex.org/W2809950606","https://openalex.org/W4252985704","https://openalex.org/W4252993849","https://openalex.org/W2774773774","https://openalex.org/W2616524835","https://openalex.org/W2086344757","https://openalex.org/W1017999001","https://openalex.org/W2791832526","https://openalex.org/W2069684819","https://openalex.org/W2029162371"],"abstract_inverted_index":{"A":[0,158],"novel":[1],"approach":[2],"utilising":[3],"the":[4,66,87,90,129],"emerging":[5],"memristor":[6],"technology":[7,64],"is":[8,23,36,54,132,140],"introduced":[9],"for":[10],"realising":[11],"a":[12,26],"2-input":[13],"primitive":[14],"XNOR":[15,31,34,52,67,79,92,102,111,162,170],"gate.":[16,103,112,156],"This":[17],"gate":[18,35,53,68,93,163],"enables":[19],"in-memory":[20],"computing":[21],"and":[22,56,84,99,120,126,128,138],"used":[24],"as":[25],"building":[27],"block":[28],"of":[29,41,49,89,96,107,135,152],"multi-input":[30,159],"gates.":[32,80],"The":[33,45],"realised":[37,61],"with":[38,58,62,78],"eight":[39],"memristors":[40,118],"two":[42,169],"crossbar":[43],"arrays.":[44],"average":[46],"power":[47],"consumption":[48],"an":[50],"8-input":[51],"calculated":[55,141],"compared":[57],"its":[59],"counterpart":[60],"CMOS":[63,173],"\u2013":[65],"consumes":[69],"less":[70],"power.":[71],"ESOP":[72],"realisation":[73],"can":[74,164],"be":[75,165],"directly":[76],"implemented":[77,166],"Our":[81],"simulation":[82],"results":[83],"comparisons":[85],"show":[86],"benefit":[88],"proposed":[91],"in":[94],"terms":[95],"delay,":[97],"area,":[98],"power.Volistor":[100],"logic":[101,110,155,161],"(a)":[104],"Circuit":[105],"diagram":[106,151],"two-input":[108,153],"volistor":[109,154,160],"Input":[113],"voltages":[114],"are":[115],"applied":[116],"to":[117,145],"S1":[119,137],"S2":[121,139],"through":[122],"horizontal":[123],"wires":[124],"Win1":[125],"Win2,":[127],"output":[130],"which":[131],"logical":[133],"AND":[134],"states":[136],"by":[142,167],"applying":[143],"VREAD":[144],"vertical":[146],"wire":[147],"WXNOR.":[148],"(b)":[149],"Block":[150],"(c)":[157],"connecting":[168],"gates":[171],"though":[172],"switches.":[174]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}