{"id":"https://openalex.org/W2160940117","doi":"https://doi.org/10.1080/10655140290011177","title":"Word\u2010serial Architectures for Filtering and Variable Rate Decimation","display_name":"Word\u2010serial Architectures for Filtering and Variable Rate Decimation","publication_year":2001,"publication_date":"2001-01-02","ids":{"openalex":"https://openalex.org/W2160940117","doi":"https://doi.org/10.1080/10655140290011177","mag":"2160940117"},"language":"en","primary_location":{"id":"doi:10.1080/10655140290011177","is_oa":true,"landing_page_url":"https://doi.org/10.1080/10655140290011177","pdf_url":"http://downloads.hindawi.com/archive/2002/805245.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"http://downloads.hindawi.com/archive/2002/805245.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023398291","display_name":"Eugene Grayver","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111107","display_name":"Integrated Laboratory Systems, Inc.","ror":"https://ror.org/020hchp05","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210111107"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eugene Grayver","raw_affiliation_strings":["Wireless Integrated Systems Laboratory, Electrical Engineering Department, 56-425B Eng. IV Bldg., UCLA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Wireless Integrated Systems Laboratory, Electrical Engineering Department, 56-425B Eng. IV Bldg., UCLA","institution_ids":["https://openalex.org/I4210111107"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001218651","display_name":"Babak Daneshrad","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111107","display_name":"Integrated Laboratory Systems, Inc.","ror":"https://ror.org/020hchp05","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210111107"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Babak Daneshrad","raw_affiliation_strings":["Wireless Integrated Systems Laboratory, Electrical Engineering Department, 56-425B Eng. IV Bldg., UCLA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Wireless Integrated Systems Laboratory, Electrical Engineering Department, 56-425B Eng. IV Bldg., UCLA","institution_ids":["https://openalex.org/I4210111107"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5001218651"],"corresponding_institution_ids":["https://openalex.org/I4210111107"],"apc_list":null,"apc_paid":null,"fwci":0.9399,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.77782765,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":"4","first_page":"363","last_page":"372"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/decimation","display_name":"Decimation","score":0.8578534722328186},{"id":"https://openalex.org/keywords/polyphase-system","display_name":"Polyphase system","score":0.7905153036117554},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6876957416534424},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6342583894729614},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.5800600647926331},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5726644396781921},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.49944281578063965},{"id":"https://openalex.org/keywords/word","display_name":"Word (group theory)","score":0.46161186695098877},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43794065713882446},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.435871958732605},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41072535514831543},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1876765787601471},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1776377558708191}],"concepts":[{"id":"https://openalex.org/C173642442","wikidata":"https://www.wikidata.org/wiki/Q1253346","display_name":"Decimation","level":3,"score":0.8578534722328186},{"id":"https://openalex.org/C96157337","wikidata":"https://www.wikidata.org/wiki/Q391639","display_name":"Polyphase system","level":2,"score":0.7905153036117554},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6876957416534424},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6342583894729614},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.5800600647926331},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5726644396781921},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.49944281578063965},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.46161186695098877},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43794065713882446},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.435871958732605},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41072535514831543},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1876765787601471},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1776377558708191},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1080/10655140290011177","is_oa":true,"landing_page_url":"https://doi.org/10.1080/10655140290011177","pdf_url":"http://downloads.hindawi.com/archive/2002/805245.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1080/10655140290011177","is_oa":true,"landing_page_url":"https://doi.org/10.1080/10655140290011177","pdf_url":"http://downloads.hindawi.com/archive/2002/805245.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2160940117.pdf","grobid_xml":"https://content.openalex.org/works/W2160940117.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W1481646516","https://openalex.org/W1897343572","https://openalex.org/W2014996247","https://openalex.org/W2102339714","https://openalex.org/W2103650311","https://openalex.org/W2110118803","https://openalex.org/W2114811723","https://openalex.org/W2119030040","https://openalex.org/W2134209173","https://openalex.org/W2136398141","https://openalex.org/W2166440210","https://openalex.org/W6675453706"],"related_works":["https://openalex.org/W2384154497","https://openalex.org/W2148631971","https://openalex.org/W3134042881","https://openalex.org/W2536077922","https://openalex.org/W2096299862","https://openalex.org/W1575732032","https://openalex.org/W1922259324","https://openalex.org/W2252272481","https://openalex.org/W2111757464","https://openalex.org/W2351767365"],"abstract_inverted_index":{"A":[0],"new":[1],"flexible":[2],"architecture":[3,14,92],"is":[4,15,28],"proposed":[5],"for":[6,17,31,67],"word\u2010serial":[7],"filtering":[8],"and":[9,27,45,54,72,81,102],"variable":[10],"rate":[11,26],"decimation/interpolation.":[12],"The":[13,76,91],"targeted":[16],"low":[18,24,46],"power":[19,47,68],"applications":[20],"requiring":[21],"medium":[22],"to":[23],"data":[25],"ideally":[29],"suited":[30],"implementation":[32],"on":[33],"either":[34],"an":[35,38,49],"ASIC":[36,50],"or":[37],"FPGA.":[39],"It":[40],"combines":[41],"the":[42,52,65],"small":[43],"size":[44],"of":[48,56,95],"with":[51],"programmability":[53],"flexibility":[55],"a":[57],"DSP.":[58],"An":[59],"efficient":[60],"memory":[61],"addressing":[62],"scheme":[63],"eliminates":[64],"need":[66],"hungry":[69],"shift":[70],"registers":[71],"allows":[73],"full":[74],"reconfiguration.":[75],"decimation":[77],"ratio,":[78],"filter":[79,82],"length":[80],"coefficients":[83],"can":[84],"all":[85],"be":[86],"changed":[87],"in":[88,98,103],"real":[89],"time.":[90],"takes":[93],"advantage":[94],"coefficient":[96],"symmetries":[97],"linear":[99],"phase":[100],"filters":[101],"polyphase":[104],"components.":[105]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}