{"id":"https://openalex.org/W2085451066","doi":"https://doi.org/10.1080/1065514021000012237","title":"CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization","display_name":"CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization","publication_year":2002,"publication_date":"2002-01-01","ids":{"openalex":"https://openalex.org/W2085451066","doi":"https://doi.org/10.1080/1065514021000012237","mag":"2085451066"},"language":"en","primary_location":{"id":"doi:10.1080/1065514021000012237","is_oa":true,"landing_page_url":"https://doi.org/10.1080/1065514021000012237","pdf_url":"https://downloads.hindawi.com/archive/2002/382497.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2002/382497.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100381300","display_name":"Sang Ho Lee","orcid":"https://orcid.org/0000-0002-4954-3861"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sangho Lee","raw_affiliation_strings":["Agere Systems, 7777 Center Avenue #300"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Agere Systems, 7777 Center Avenue #300","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044924448","display_name":"E.W. Greeneich","orcid":null},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edwin W. Greeneich","raw_affiliation_strings":["Electrical Department, Arizona State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Department, Arizona State University","institution_ids":["https://openalex.org/I55732556"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15565661,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"15","issue":"3","first_page":"619","last_page":"628"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.735159695148468},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7074822783470154},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6048938035964966},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5700742602348328},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45734357833862305},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3748677968978882},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3673279285430908},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.33783239126205444},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28983649611473083},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1280178725719452},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08128246665000916},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.06101730465888977}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.735159695148468},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7074822783470154},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6048938035964966},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5700742602348328},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45734357833862305},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3748677968978882},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3673279285430908},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.33783239126205444},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28983649611473083},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1280178725719452},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08128246665000916},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.06101730465888977},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1080/1065514021000012237","is_oa":true,"landing_page_url":"https://doi.org/10.1080/1065514021000012237","pdf_url":"https://downloads.hindawi.com/archive/2002/382497.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},{"id":"pmh:oai:doaj.org/article:84bb0de79c2947adaea2be223f1cebcf","is_oa":false,"landing_page_url":"https://doaj.org/article/84bb0de79c2947adaea2be223f1cebcf","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"VLSI Design, Vol 15, Iss 3, Pp 619-628 (2002)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1080/1065514021000012237","is_oa":true,"landing_page_url":"https://doi.org/10.1080/1065514021000012237","pdf_url":"https://downloads.hindawi.com/archive/2002/382497.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2085451066.pdf","grobid_xml":"https://content.openalex.org/works/W2085451066.grobid-xml"},"referenced_works_count":10,"referenced_works":["https://openalex.org/W1984588379","https://openalex.org/W2055510065","https://openalex.org/W2097749440","https://openalex.org/W2102256773","https://openalex.org/W2135250302","https://openalex.org/W2142992648","https://openalex.org/W2145269393","https://openalex.org/W2147527731","https://openalex.org/W2174953611","https://openalex.org/W4242232915"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W3014521742","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2109445684","https://openalex.org/W2081082331"],"abstract_inverted_index":{"Efficient,":[0],"generalized":[1],"delay":[2],"and":[3,14,19,38,53,63],"power":[4],"equations":[5,26,43],"are":[6,27,74],"proposed":[7,24],"for":[8],"large":[9],"scale":[10],"CMOS":[11,61,72],"circuit":[12,62],"analysis":[13],"optimization":[15,50],"achieved":[16],"by":[17],"transistor":[18,52],"interconnect":[20,54],"wire":[21,55],"minimization.":[22],"The":[23],"model":[25],"used":[28],"to":[29,47],"analyze":[30],"the":[31,49],"entire":[32],"power\u2010delay":[33],"trade\u2010off":[34],"with":[35],"less":[36],"complexity":[37],"faster":[39],"computation":[40],"time.":[41],"New":[42],"can":[44],"be":[45],"adopted":[46],"perform":[48],"of":[51],"size":[56],"concurrently.":[57],"A":[58],"single":[59],"stage":[60],"a":[64],"clock":[65],"generation":[66],"block":[67],"fabricated":[68],"in":[69],"0.48":[70],"um":[71],"process":[73],"given":[75],"as":[76],"experimental":[77],"examples.":[78]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}