{"id":"https://openalex.org/W2023822548","doi":"https://doi.org/10.1080/1065514021000012066","title":"Low\u2010power Implementation of an Encryption/Decryption System with Asynchronous Techniques","display_name":"Low\u2010power Implementation of an Encryption/Decryption System with Asynchronous Techniques","publication_year":2001,"publication_date":"2001-06-21","ids":{"openalex":"https://openalex.org/W2023822548","doi":"https://doi.org/10.1080/1065514021000012066","mag":"2023822548"},"language":"en","primary_location":{"id":"doi:10.1080/1065514021000012066","is_oa":true,"landing_page_url":"https://doi.org/10.1080/1065514021000012066","pdf_url":"https://downloads.hindawi.com/archive/2002/732414.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://downloads.hindawi.com/archive/2002/732414.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Nikos Sklavos","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Nikos Sklavos","raw_affiliation_strings":["Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103718660","display_name":"Alexandros Papakonstantinou","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Alexandros Papakonstantinou","raw_affiliation_strings":["Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020277934","display_name":"S. Theoharis","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Spyros Theoharis","raw_affiliation_strings":["Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090802119","display_name":"Odysseas Koufopavlou","orcid":"https://orcid.org/0000-0002-6287-7073"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Odysseas Koufopavlou","raw_affiliation_strings":["Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.4359,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.68244781,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"15","issue":"1","first_page":"455","last_page":"468"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8630850315093994},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7936794757843018},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7830196619033813},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.6437930464744568},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5719583034515381},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.513869047164917},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4351904094219208},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4333832561969757},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4093254804611206},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37321147322654724},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.21052652597427368},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.18804731965065002},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15988469123840332},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12306323647499084}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8630850315093994},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7936794757843018},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7830196619033813},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.6437930464744568},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5719583034515381},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.513869047164917},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4351904094219208},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4333832561969757},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4093254804611206},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37321147322654724},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.21052652597427368},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.18804731965065002},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15988469123840332},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12306323647499084},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1080/1065514021000012066","is_oa":true,"landing_page_url":"https://doi.org/10.1080/1065514021000012066","pdf_url":"https://downloads.hindawi.com/archive/2002/732414.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1080/1065514021000012066","is_oa":true,"landing_page_url":"https://doi.org/10.1080/1065514021000012066","pdf_url":"https://downloads.hindawi.com/archive/2002/732414.pdf","source":{"id":"https://openalex.org/S81291924","display_name":"VLSI design","issn_l":"1026-7123","issn":["1026-7123","1065-514X","1563-5171"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319869","host_organization_name":"Hindawi Publishing Corporation","host_organization_lineage":["https://openalex.org/P4310319869"],"host_organization_lineage_names":["Hindawi Publishing Corporation"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"VLSI Design","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.6600000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2023822548.pdf","grobid_xml":"https://content.openalex.org/works/W2023822548.grobid-xml"},"referenced_works_count":23,"referenced_works":["https://openalex.org/W1529845771","https://openalex.org/W1534625052","https://openalex.org/W1605116544","https://openalex.org/W1969855192","https://openalex.org/W1978695162","https://openalex.org/W2101996506","https://openalex.org/W2104486720","https://openalex.org/W2106013742","https://openalex.org/W2113399386","https://openalex.org/W2118702985","https://openalex.org/W2121914493","https://openalex.org/W2129441466","https://openalex.org/W2132283882","https://openalex.org/W2140591466","https://openalex.org/W2145654204","https://openalex.org/W2150908879","https://openalex.org/W2158463352","https://openalex.org/W3143840390","https://openalex.org/W3151011186","https://openalex.org/W3204802657","https://openalex.org/W4241679623","https://openalex.org/W6678153968","https://openalex.org/W6679630453"],"related_works":["https://openalex.org/W2049402143","https://openalex.org/W2110818533","https://openalex.org/W1948903516","https://openalex.org/W1993985975","https://openalex.org/W2146990170","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2085028021","https://openalex.org/W2138474603","https://openalex.org/W2355622827"],"abstract_inverted_index":{"An":[0],"asynchronous":[1,21,111,120],"VLSI":[2],"implementation":[3,95,112],"of":[4,26,72,81,96,109],"the":[5,20,27,42,50,84,93,97,105,110,115,119],"International":[6],"Data":[7],"Encryption":[8,126],"Algorithm":[9],"(IDEA)":[10],"is":[11],"presented":[12],"in":[13,38,124],"this":[14],"paper.":[15],"In":[16],"order":[17,39],"to":[18,40,74,114],"evaluate":[19],"design":[22],"a":[23,69,78],"synchronous":[24],"version":[25],"algorithm":[28],"was":[29,36,53],"also":[30],"designed.":[31],"VHDL":[32,51],"hardware":[33],"description":[34],"language":[35],"used":[37],"describe":[41],"algorithm.":[43,99],"By":[44],"using":[45],"Synopsys":[46],"commercial":[47],"available":[48],"tools":[49],"code":[52],"synthesized.":[54],"After":[55],"placing":[56],"and":[57,77,89,128],"routing":[58],"both":[59],"designs":[60],"were":[61,87],"fabricated":[62],"with":[63,92],"0.6":[64],"\u03bcm":[65],"CMOS":[66],"technology.":[67],"With":[68],"system":[70],"clock":[71],"up":[73],"8":[75],"MHz":[76],"power":[79,107],"supply":[80],"5":[82],"V":[83],"two":[85],"chips":[86],"tested":[88],"evaluated":[90],"comparing":[91],"software":[94],"IDEA":[98],"This":[100],"new":[101],"approach":[102],"proves":[103],"efficiently":[104,123],"lowest":[106],"consumption":[108],"compared":[113],"existing":[116],"synchronous.":[117],"Therefore,":[118],"chip":[121],"performs":[122],"Wireless":[125],"Protocols":[127],"high":[129],"speed":[130],"networks.":[131]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}