{"id":"https://openalex.org/W2049284689","doi":"https://doi.org/10.1080/10637199508915530","title":"MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION","display_name":"MODULAR FIXED-SIZE VLSI ARCHITECTURES FOR GENERAL MULTISPLITTING ITERATION","publication_year":1995,"publication_date":"1995-01-01","ids":{"openalex":"https://openalex.org/W2049284689","doi":"https://doi.org/10.1080/10637199508915530","mag":"2049284689"},"language":"en","primary_location":{"id":"doi:10.1080/10637199508915530","is_oa":false,"landing_page_url":"https://doi.org/10.1080/10637199508915530","pdf_url":null,"source":{"id":"https://openalex.org/S89732838","display_name":"Parallel algorithms and applications","issn_l":"1026-7689","issn":["1026-7689","1029-032X","1063-7192"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Algorithms and Applications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103334666","display_name":"Elena P. Papadopoulou","orcid":null},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"ELENA PAPADOPOULOU","raw_affiliation_strings":["\n Applied Math and Computers Lab, Technical University of Crete, Chania 73100, Crete, Greece","Applied Math and Computers Lab, Technical University of Crete , Chania 73100, Crete, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\n Applied Math and Computers Lab, Technical University of Crete, Chania 73100, Crete, Greece","institution_ids":["https://openalex.org/I55741626"]},{"raw_affiliation_string":"Applied Math and Computers Lab, Technical University of Crete , Chania 73100, Crete, Greece","institution_ids":["https://openalex.org/I55741626"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066823983","display_name":"Yiannis G. Saridakis","orcid":"https://orcid.org/0000-0002-2992-3883"},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"YIANNIS SARIDAKIS","raw_affiliation_strings":["\n Applied Math and Computers Lab, Technical University of Crete, Chania 73100, Crete, Greece","Applied Math and Computers Lab, Technical University of Crete , Chania 73100, Crete, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\n Applied Math and Computers Lab, Technical University of Crete, Chania 73100, Crete, Greece","institution_ids":["https://openalex.org/I55741626"]},{"raw_affiliation_string":"Applied Math and Computers Lab, Technical University of Crete , Chania 73100, Crete, Greece","institution_ids":["https://openalex.org/I55741626"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17962003,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"3-4","first_page":"177","last_page":"191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10792","display_name":"Matrix Theory and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10792","display_name":"Matrix Theory and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8222388029098511},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6958838701248169},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6164038181304932},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5933032631874084},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5839018821716309},{"id":"https://openalex.org/keywords/factorization","display_name":"Factorization","score":0.5615886449813843},{"id":"https://openalex.org/keywords/iterative-method","display_name":"Iterative method","score":0.45413216948509216},{"id":"https://openalex.org/keywords/lu-decomposition","display_name":"LU decomposition","score":0.4266376793384552},{"id":"https://openalex.org/keywords/matrix-decomposition","display_name":"Matrix decomposition","score":0.41978126764297485},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31596142053604126},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0914231538772583},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.07750740647315979}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8222388029098511},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6958838701248169},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6164038181304932},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5933032631874084},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5839018821716309},{"id":"https://openalex.org/C187834632","wikidata":"https://www.wikidata.org/wiki/Q188804","display_name":"Factorization","level":2,"score":0.5615886449813843},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.45413216948509216},{"id":"https://openalex.org/C123213974","wikidata":"https://www.wikidata.org/wiki/Q833089","display_name":"LU decomposition","level":4,"score":0.4266376793384552},{"id":"https://openalex.org/C42355184","wikidata":"https://www.wikidata.org/wiki/Q1361088","display_name":"Matrix decomposition","level":3,"score":0.41978126764297485},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31596142053604126},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0914231538772583},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.07750740647315979},{"id":"https://openalex.org/C158693339","wikidata":"https://www.wikidata.org/wiki/Q190524","display_name":"Eigenvalues and eigenvectors","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1080/10637199508915530","is_oa":false,"landing_page_url":"https://doi.org/10.1080/10637199508915530","pdf_url":null,"source":{"id":"https://openalex.org/S89732838","display_name":"Parallel algorithms and applications","issn_l":"1026-7689","issn":["1026-7689","1029-032X","1063-7192"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Algorithms and Applications","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W114716186","https://openalex.org/W275521141","https://openalex.org/W1509443229","https://openalex.org/W1512483332","https://openalex.org/W1574923065","https://openalex.org/W1575413677","https://openalex.org/W1820065643","https://openalex.org/W1970105169","https://openalex.org/W1970261865","https://openalex.org/W1975563825","https://openalex.org/W2009055506","https://openalex.org/W2017369466","https://openalex.org/W2022817956","https://openalex.org/W2040436966","https://openalex.org/W2054388411","https://openalex.org/W2058585078","https://openalex.org/W2058698834","https://openalex.org/W2064130185","https://openalex.org/W2080275298","https://openalex.org/W2083883802","https://openalex.org/W2092863163","https://openalex.org/W2110945399","https://openalex.org/W2138245082","https://openalex.org/W2139378242","https://openalex.org/W2467964844","https://openalex.org/W2561675875","https://openalex.org/W2588081979","https://openalex.org/W2798909945","https://openalex.org/W2995746888","https://openalex.org/W4285719527","https://openalex.org/W4290044953","https://openalex.org/W4299343067"],"related_works":["https://openalex.org/W2766762530","https://openalex.org/W119752240","https://openalex.org/W2602301532","https://openalex.org/W1988437637","https://openalex.org/W1977700955","https://openalex.org/W4388311419","https://openalex.org/W2271643833","https://openalex.org/W1973739845","https://openalex.org/W2127054029","https://openalex.org/W2060455298"],"abstract_inverted_index":{"Abstract":[0],"Motivated":[1],"by":[2],"the":[3,7,16,32,39,66,76,79,84,90,93],"inherent":[4],"parallelicity":[5],"of":[6,18,26,34,41,62,78,92],"Multisplitting":[8],"Iterative":[9],"Methods,":[10],"we":[11,45,51,82,96],"consider":[12],"their":[13],"application":[14],"for":[15,89],"solution":[17],"Large":[19],"Linear":[20],"Systems.":[21],"The":[22],"realistic":[23],"parallel":[24],"implementation":[25],"this":[27],"problem":[28],"led":[29],"us":[30],"to":[31,57],"employment":[33],"fixed-size":[35,59],"VLSI":[36,54],"architectures.":[37],"Considering":[38],"case":[40],"General":[42],"Splitting":[43],"matrices":[44,81],"combine":[46],"known":[47],"as":[48,50],"well":[49],"design":[52],"new":[53],"BLAS":[55],"modules":[56],"form":[58],"architectures":[60],"capable":[61],"efficiently":[63],"carrying":[64],"out":[65],"computations":[67],"involved":[68],"in":[69],"an":[70],"oversized":[71],"multisplitting":[72],"iteration":[73],"step.":[74],"For":[75],"factorization":[77],"splitting":[80],"employ":[83],"LU":[85],"decomposition":[86],"method":[87],"while":[88],"organization":[91],"data":[94],"streams":[95],"use":[97],"space-time":[98],"partitioning":[99],"techniques.":[100],"KEY":[101],"WORDS:":[102],"Systolic":[103],"algorithmsVLSI":[104],"architecturesiterative":[105],"methodsC.R.":[106],"CATEGORIES:":[107],"C.2.1G.1.3":[108]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}