{"id":"https://openalex.org/W2073399389","doi":"https://doi.org/10.1049/iet-cdt:20060175","title":"Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems","display_name":"Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems","publication_year":2008,"publication_date":"2008-04-17","ids":{"openalex":"https://openalex.org/W2073399389","doi":"https://doi.org/10.1049/iet-cdt:20060175","mag":"2073399389"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cdt:20060175","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20060175","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers & Digital Techniques","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research-information.bris.ac.uk/en/publications/093072b9-87a8-4d93-9d80-40296d1ed774","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005255540","display_name":"Jose Nunez\u2010Yanez","orcid":"https://orcid.org/0000-0002-5153-5481"},"institutions":[{"id":"https://openalex.org/I36234482","display_name":"University of Bristol","ror":"https://ror.org/0524sp257","country_code":"GB","type":"education","lineage":["https://openalex.org/I36234482"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"J.L. Nunez-Yanez","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Bristol University, Woodland Road, Bristol, BS8 1UB, UK","Microelectronics"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Bristol University, Woodland Road, Bristol, BS8 1UB, UK","institution_ids":["https://openalex.org/I36234482"]},{"raw_affiliation_string":"Microelectronics","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108435403","display_name":"D. Edwards","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D. Edwards","raw_affiliation_strings":["School of Computer Science, University of Manchester, Oxford Road, Manchester, M13 9PL, UK","University of Manchester\u00a0"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Oxford Road, Manchester, M13 9PL, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"University of Manchester\u00a0","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021619024","display_name":"Antonio Coppola","orcid":"https://orcid.org/0000-0001-6538-6184"},"institutions":[{"id":"https://openalex.org/I131827901","display_name":"STMicroelectronics (Switzerland)","ror":"https://ror.org/00wm3b005","country_code":"CH","type":"company","lineage":["https://openalex.org/I131827901"]},{"id":"https://openalex.org/I4210124177","display_name":"STMicroelectronics (Czechia)","ror":"https://ror.org/03c7ss521","country_code":"CZ","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210124177"]}],"countries":["CH","CZ"],"is_corresponding":false,"raw_author_name":"A.M. Coppola","raw_affiliation_strings":["STMicroelectronics, 12, rue Jules Horowith, Grenoble, 38019, France","STMicroelectronics"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, 12, rue Jules Horowith, Grenoble, 38019, France","institution_ids":["https://openalex.org/I131827901"]},{"raw_affiliation_string":"STMicroelectronics","institution_ids":["https://openalex.org/I4210124177"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5005255540"],"corresponding_institution_ids":["https://openalex.org/I36234482"],"apc_list":{"value":2000,"currency":"EUR","value_usd":2200},"apc_paid":null,"fwci":4.2356,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.94365666,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"2","issue":"3","first_page":"184","last_page":"198"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10018","display_name":"Advancements in Battery Materials","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6515647172927856},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.6309729814529419},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6079132556915283},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5909984111785889},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5909308791160583},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.5451180338859558},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.535120964050293},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5229806900024414},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4888302683830261},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.4877684712409973},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4393364489078522},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4294447898864746},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.41771888732910156},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34781700372695923},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3079286217689514},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22549524903297424},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.1945495903491974}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6515647172927856},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.6309729814529419},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6079132556915283},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5909984111785889},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5909308791160583},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5451180338859558},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.535120964050293},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5229806900024414},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4888302683830261},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4877684712409973},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4393364489078522},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4294447898864746},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.41771888732910156},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34781700372695923},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3079286217689514},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22549524903297424},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.1945495903491974},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1049/iet-cdt:20060175","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20060175","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers & Digital Techniques","raw_type":"journal-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/587800eb-c97b-4fdb-a522-bd1374a0b6ce","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/587800eb-c97b-4fdb-a522-bd1374a0b6ce","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Nunez-Yanez, J L, Edwards, D & Coppola, A M 2008, 'Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems', IET Computers and Digital Techniques, vol. 2, no. 3, pp. 184-198. https://doi.org/10.1049/iet-cdt:20060175","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:research-information.bris.ac.uk:openaire_cris_publications/093072b9-87a8-4d93-9d80-40296d1ed774","is_oa":true,"landing_page_url":"https://research-information.bris.ac.uk/en/publications/093072b9-87a8-4d93-9d80-40296d1ed774","pdf_url":null,"source":{"id":"https://openalex.org/S7407055359","display_name":"Explore Bristol Research","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Nunez-Yanez, JL, Edwards, D & Coppola, AM 2008, 'Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems', IET Computers and Digital Techniques, vol. 2 , no. 3, pp. 184 - 198. https://doi.org/10.1049/iet-cdt:20060175","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:pure.atira.dk:publications/587800eb-c97b-4fdb-a522-bd1374a0b6ce","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/adaptive-routing-strategies-for-faulttolerant-onchip-networks-in-dynamically-reconfigurable-systems(587800eb-c97b-4fdb-a522-bd1374a0b6ce).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Nunez-Yanez, J L, Edwards, D & Coppola, A M 2008, 'Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems', IET Computers and Digital Techniques, vol. 2, no. 3, pp. 184-198. https://doi.org/10.1049/iet-cdt:20060175","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:research-information.bris.ac.uk:publications/093072b9-87a8-4d93-9d80-40296d1ed774","is_oa":false,"landing_page_url":"https://hdl.handle.net/1983/093072b9-87a8-4d93-9d80-40296d1ed774","pdf_url":null,"source":{"id":"https://openalex.org/S4306400895","display_name":"Bristol Research (University of Bristol)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I36234482","host_organization_name":"University of Bristol","host_organization_lineage":["https://openalex.org/I36234482"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":{"id":"pmh:oai:research-information.bris.ac.uk:openaire_cris_publications/093072b9-87a8-4d93-9d80-40296d1ed774","is_oa":true,"landing_page_url":"https://research-information.bris.ac.uk/en/publications/093072b9-87a8-4d93-9d80-40296d1ed774","pdf_url":null,"source":{"id":"https://openalex.org/S7407055359","display_name":"Explore Bristol Research","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Nunez-Yanez, JL, Edwards, D & Coppola, AM 2008, 'Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems', IET Computers and Digital Techniques, vol. 2 , no. 3, pp. 184 - 198. https://doi.org/10.1049/iet-cdt:20060175","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G2532943134","display_name":null,"funder_award_id":"EP/E062164/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1668025881","https://openalex.org/W1946139549","https://openalex.org/W2031273683","https://openalex.org/W2031933249","https://openalex.org/W2032661585","https://openalex.org/W2035560780","https://openalex.org/W2096069498","https://openalex.org/W2106783962","https://openalex.org/W2117520286","https://openalex.org/W2126350230","https://openalex.org/W2132719761","https://openalex.org/W2135113699","https://openalex.org/W2146491924","https://openalex.org/W2147446937","https://openalex.org/W2158051804","https://openalex.org/W2160642395","https://openalex.org/W2169213530","https://openalex.org/W2169731778","https://openalex.org/W2537451884","https://openalex.org/W2544644419","https://openalex.org/W2554621958"],"related_works":["https://openalex.org/W2326041751","https://openalex.org/W2189025524","https://openalex.org/W2388289950","https://openalex.org/W1988994136","https://openalex.org/W2008643752","https://openalex.org/W2967532063","https://openalex.org/W1972431215","https://openalex.org/W2518903510","https://openalex.org/W2080975550","https://openalex.org/W2009731420"],"abstract_inverted_index":{"An":[0],"investigation":[1],"into":[2],"an":[3,15,128],"effective":[4],"and":[5,35,47,67,74,78,114,117],"low-complexity":[6],"adaptive":[7],"routing":[8,34],"strategy":[9],"based":[10],"on":[11],"stochastic":[12],"principles":[13],"for":[14,133],"asynchronous":[16],"network-on-chip":[17],"platform":[18],"that":[19,63,92],"includes":[20],"dynamically":[21],"reconfigurable":[22],"computing":[23],"nodes":[24],"is":[25,29,37,58,90],"presented.":[26],"The":[27,51],"approach":[28],"compared":[30],"with":[31],"classic":[32],"deterministic":[33,87],"it":[36],"shown":[38],"to":[39,55,84,107],"have":[40],"good":[41],"properties":[42],"in":[43],"terms":[44],"of":[45,53,60,96],"throughput":[46],"excellent":[48],"fault-tolerance":[49],"capabilities.":[50],"challenge":[52],"how":[54],"deliver":[56,108],"reliability":[57],"one":[59],"the":[61,82,125],"problems":[62],"multiprocessor":[64],"system":[65],"architects":[66],"manufactures":[68],"will":[69,101,104],"face":[70],"as":[71],"feature":[72],"sizes":[73],"voltage":[75],"supplies":[76],"shrink":[77],"deep-submicron":[79,97],"effects":[80],"reduce":[81],"ability":[83],"carry":[85],"out":[86],"computing.":[88],"It":[89],"likely":[91],"a":[93],"new":[94],"type":[95],"complex":[98],"multicore":[99],"systems":[100],"emerge":[102],"which":[103],"be":[105],"required":[106],"high":[109],"performance":[110],"within":[111],"strict":[112],"energy":[113],"area":[115],"budgets":[116],"operate":[118],"over":[119],"unreliable":[120],"silicon.":[121],"Within":[122],"this":[123],"context,":[124],"paper":[126],"studies":[127],"on-chip":[129],"communication":[130],"infrastructure":[131],"suitable":[132],"these":[134],"systems.":[135]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-03-15T09:29:46.208133","created_date":"2025-10-10T00:00:00"}