{"id":"https://openalex.org/W1988748737","doi":"https://doi.org/10.1049/iet-cdt:20060016","title":"ROM to DSP block transfer for resource constrained synthesis","display_name":"ROM to DSP block transfer for resource constrained synthesis","publication_year":2007,"publication_date":"2007-01-09","ids":{"openalex":"https://openalex.org/W1988748737","doi":"https://doi.org/10.1049/iet-cdt:20060016","mag":"1988748737"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cdt:20060016","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20060016","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers &amp; Digital Techniques","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084087951","display_name":"Gareth W. Morris","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"G.W. Morris","raw_affiliation_strings":["Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"G.A. Constantinides","raw_affiliation_strings":["Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"P.Y.K. Cheung","raw_affiliation_strings":["Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK"],"affiliations":[{"raw_affiliation_string":"Circuits and Systems Group, Department of Electronic and Electrical Engineering, Imperial College, Exhibition Road, London, SW7 2BT, UK","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5084087951"],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":{"value":2000,"currency":"EUR","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06253107,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":"1","first_page":"17","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8375823497772217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7727000117301941},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6852868795394897},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.679473876953125},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6427012085914612},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5849497318267822},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.579089879989624},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.5018002986907959},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4556042551994324},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4284578263759613},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.42067837715148926},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4143680930137634},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4074973464012146},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3985472619533539},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36561793088912964},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.14978066086769104},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12024164199829102}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8375823497772217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7727000117301941},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6852868795394897},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.679473876953125},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6427012085914612},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5849497318267822},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.579089879989624},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.5018002986907959},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4556042551994324},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4284578263759613},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.42067837715148926},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4143680930137634},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4074973464012146},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3985472619533539},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36561793088912964},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.14978066086769104},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12024164199829102},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/iet-cdt:20060016","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20060016","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers &amp; Digital Techniques","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6672801631","display_name":null,"funder_award_id":"EP/E00024X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1480183640","https://openalex.org/W1500238730","https://openalex.org/W1545238850","https://openalex.org/W1549614911","https://openalex.org/W1600183590","https://openalex.org/W1649344707","https://openalex.org/W1767781815","https://openalex.org/W1787437284","https://openalex.org/W1977966390","https://openalex.org/W2056760934","https://openalex.org/W2058775467","https://openalex.org/W2099089225","https://openalex.org/W2111730172","https://openalex.org/W2143943882","https://openalex.org/W2144736151","https://openalex.org/W2153575635","https://openalex.org/W4235346344","https://openalex.org/W6629867105"],"related_works":["https://openalex.org/W4241206086","https://openalex.org/W2109697164","https://openalex.org/W1528726807","https://openalex.org/W1964556228","https://openalex.org/W809008615","https://openalex.org/W4312121094","https://openalex.org/W3047975009","https://openalex.org/W2156420848","https://openalex.org/W1905101075","https://openalex.org/W2543290882"],"abstract_inverted_index":{"Modern":[0],"field":[1],"programmable":[2],"gate":[3],"array":[4],"(FPGA)":[5],"architectures":[6],"are":[7],"moving":[8],"towards":[9],"heterogeneity":[10],"with":[11,183],"the":[12,40,78,123,151,170,184,191,194],"increasing":[13],"inclusion":[14],"of":[15,34,46,89,125,169,196],"coarse":[16],"grained":[17],"elements":[18,58,69],"such":[19],"as":[20],"embedded":[21,95],"multipliers":[22],"and":[23,85,97,139],"RAMs.":[24],"This":[25],"has":[26,199],"given":[27],"rise":[28],"to":[29,54,114,134,150,187,203],"a":[30,52,73,119,130],"multi-dimensioned":[31],"resource-based":[32],"measure":[33],"design":[35,74,131],"area,":[36],"very":[37],"different":[38],"from":[39,179],"traditional":[41],"application-specific":[42],"integrated":[43],"circuit":[44],"figure":[45],"silicon":[47,83],"area.":[48],"In":[49,190],"order":[50],"for":[51],"designer":[53],"use":[55],"these":[56],"heterogenous":[57,143],"in":[59,72,94,118,167],"their":[60],"design,":[61],"they":[62],"must":[63],"usually":[64],"specifically":[65],"instantiate":[66],"them.":[67],"Heterogeneous":[68],"not":[70],"used":[71],"remain":[75],"unused":[76,103],"on":[77,142,147],"device,":[79],"consuming":[80],"leakage":[81],"power,":[82],"area":[84],"manufacturing":[86],"costs.":[87],"Method":[88],"transferring":[90],"functionality":[91],"normally":[92],"implemented":[93],"ROMs":[96,172],"4-input":[98],"look-up":[99],"tables":[100],"(4-LUTs)":[101],"onto":[102],"digital":[104],"signal":[105],"processor":[106],"(DSP)":[107],"blocks":[108],"is":[109,132],"proposed.":[110],"The":[111],"paper":[112],"proceeds":[113],"include":[115],"this":[116,181],"method":[117],"synthesis":[120,155,185],"system":[121,186],"incorporating":[122],"idea":[124],"resource":[126],"constrained":[127],"synthesis,":[128],"where":[129],"mapped":[133],"an":[135,148,162],"FPGA":[136],"considering":[137],"user":[138],"device":[140],"constraints":[141],"element":[144],"usage,":[145],"based":[146],"extension":[149],"Altera":[152,207],"Quartus":[153],"II":[154],"software.":[156],"Results":[157],"have":[158,176],"been":[159,177],"obtained,":[160],"showing":[161],"improvement":[163],"over":[164,206],"existing":[165],"methods":[166],"76%":[168],"21":[171],"examined.":[173],"Further":[174],"results":[175],"obtained":[178],"applying":[180],"approach":[182],"benchmark":[188],"algorithms.":[189],"designs":[192],"examined,":[193],"number":[195],"possible":[197],"implementations":[198],"increased":[200],"by":[201],"two":[202],"four":[204],"times":[205],"Quartus.":[208]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
