{"id":"https://openalex.org/W1964119810","doi":"https://doi.org/10.1049/iet-cdt:20050213","title":"Modelling tools built upon the hardware description language foundation","display_name":"Modelling tools built upon the hardware description language foundation","publication_year":2007,"publication_date":"2007-09-04","ids":{"openalex":"https://openalex.org/W1964119810","doi":"https://doi.org/10.1049/iet-cdt:20050213","mag":"1964119810"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cdt:20050213","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20050213","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers &amp; Digital Techniques","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109343494","display_name":"Alan Mantooth","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Mantooth","raw_affiliation_strings":["Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080866739","display_name":"A. Matthew Francis","orcid":"https://orcid.org/0000-0003-1102-1213"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Francis","raw_affiliation_strings":["Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101499148","display_name":"Yucheng Feng","orcid":"https://orcid.org/0000-0001-7748-614X"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Feng","raw_affiliation_strings":["Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005599581","display_name":"Wei Zheng","orcid":"https://orcid.org/0000-0003-0173-1326"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Zheng","raw_affiliation_strings":["University of Arkansas, USA","University of Arkansas at Fayetteville, Fayetteville, United States"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"University of Arkansas at Fayetteville, Fayetteville, United States","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109343494"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":{"value":2000,"currency":"EUR","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.06774669,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"1","issue":"5","first_page":"519","last_page":"527"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.8083831071853638},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7252962589263916},{"id":"https://openalex.org/keywords/software-portability","display_name":"Software portability","score":0.7125447988510132},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.6646884679794312},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.6557106971740723},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6448934674263},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6031287908554077},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.531649649143219},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4567983150482178},{"id":"https://openalex.org/keywords/modeling-language","display_name":"Modeling language","score":0.4425821602344513},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.4301188290119171},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42995917797088623},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.37993359565734863},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.377243310213089},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2488955855369568},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19693538546562195},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12648490071296692},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.11915343999862671},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09791821241378784}],"concepts":[{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.8083831071853638},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7252962589263916},{"id":"https://openalex.org/C63000827","wikidata":"https://www.wikidata.org/wiki/Q3080428","display_name":"Software portability","level":2,"score":0.7125447988510132},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.6646884679794312},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6557106971740723},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6448934674263},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6031287908554077},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.531649649143219},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4567983150482178},{"id":"https://openalex.org/C179603123","wikidata":"https://www.wikidata.org/wiki/Q1941921","display_name":"Modeling language","level":3,"score":0.4425821602344513},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4301188290119171},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42995917797088623},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.37993359565734863},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.377243310213089},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2488955855369568},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19693538546562195},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12648490071296692},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.11915343999862671},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09791821241378784},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/iet-cdt:20050213","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20050213","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers &amp; Digital Techniques","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1504814910","https://openalex.org/W1517072937","https://openalex.org/W1522597263","https://openalex.org/W1531329286","https://openalex.org/W1567084891","https://openalex.org/W1579174143","https://openalex.org/W2079826846","https://openalex.org/W2139387429","https://openalex.org/W2542049944","https://openalex.org/W4233702017","https://openalex.org/W6634623461"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2139058049","https://openalex.org/W2384838054","https://openalex.org/W2129583176","https://openalex.org/W2357636087","https://openalex.org/W2536306358","https://openalex.org/W2370873755","https://openalex.org/W2389698729","https://openalex.org/W1964119810"],"abstract_inverted_index":{"Hardware":[0],"description":[1],"languages":[2],"(HDLs),":[3],"mainly":[4],"Verilog":[5],"and":[6,49,91,100,108,116,121,131,139,152],"VHDL":[7],"including":[8],"their":[9],"analogue/mixed-signal":[10],"(AMS)":[11],"extensions,":[12],"represent":[13,60],"a":[14,30,61,149],"significant":[15],"investment":[16],"by":[17],"the":[18,66,76],"electronic":[19,68],"design":[20,41,44,69],"automation":[21,70],"community.":[22],"HDL":[23,77],"technology":[24],"promises":[25],"productivity":[26],"advances,":[27],"such":[28,80],"as":[29],"medium":[31],"for":[32,45,54],"intellectual":[33],"property":[34],"exchange,":[35],"model":[36,38,126],"portability,":[37],"productivity,":[39],"improved":[40,55],"collaboration,":[42],"top-down":[43],"AMS,":[46],"AMS":[47],"synthesis":[48],"rich":[50],"mixed-level,":[51],"mixed-signal":[52,119,130],"simulation":[53,56],"throughput.":[57],"Modelling":[58],"tools":[59,83],"step":[62],"towards":[63],"completion":[64],"of":[65,82,129,137,144],"dwelling":[67],"community&apos;s":[71],"seek":[72],"to":[73],"build":[74],"upon":[75],"foundation.":[78],"One":[79],"environment":[81],"described":[84,90],"here":[85],"is":[86,89,159],"Paragon.":[87],"Paragon":[88],"demonstrated":[92],"on":[93],"both":[94],"behavioural":[95,146],"models":[96,147],"using":[97,155],"multiple":[98],"HDLs":[99],"compact":[101,145],"device":[102],"modelling":[103,109,117,157],"applications.":[104],"The":[105,125],"various":[106,135],"processes":[107,128],"methodologies":[110,158],"that":[111],"are":[112,123,141],"useful":[113],"in":[114],"designing":[115],"complex":[118],"circuits":[120],"systems":[122,133],"explored.":[124],"creation":[127],"mixed-technology":[132],"at":[134,148],"levels":[136],"abstraction":[138],"hierarchy":[140],"described.":[142],"Creation":[143],"more":[150],"abstract":[151],"language-independent":[153],"level":[154],"these":[156],"illustrated.":[160]},"counts_by_year":[{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
