{"id":"https://openalex.org/W1969343040","doi":"https://doi.org/10.1049/iet-cdt:20050205","title":"Simulation and development environment for mobile 3D graphics architectures","display_name":"Simulation and development environment for mobile 3D graphics architectures","publication_year":2007,"publication_date":"2007-09-04","ids":{"openalex":"https://openalex.org/W1969343040","doi":"https://doi.org/10.1049/iet-cdt:20050205","mag":"1969343040"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cdt:20050205","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20050205","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers & Digital Techniques","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100638533","display_name":"Won\u2010Jae Lee","orcid":"https://orcid.org/0000-0002-1438-8005"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"W.-J. Lee","raw_affiliation_strings":["Media System Laboratory, Department of Computer Science, Yonsei University, College of Engineering, 134 Shinchon-Dong, Sudaemoon-Ku, Seoul, 120-749, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Media System Laboratory, Department of Computer Science, Yonsei University, College of Engineering, 134 Shinchon-Dong, Sudaemoon-Ku, Seoul, 120-749, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005295926","display_name":"W.-C. Park","orcid":null},"institutions":[{"id":"https://openalex.org/I28777354","display_name":"Sejong University","ror":"https://ror.org/00aft1q37","country_code":"KR","type":"education","lineage":["https://openalex.org/I28777354"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"W.-C. Park","raw_affiliation_strings":["School of Computer Engineering, Department of Internet Computing, Sejong Univeristy, 98 Kunja-Dong, Kwangjin-Ku, Seoul, 143-747, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Engineering, Department of Internet Computing, Sejong Univeristy, 98 Kunja-Dong, Kwangjin-Ku, Seoul, 143-747, South Korea","institution_ids":["https://openalex.org/I28777354"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030671453","display_name":"Vason P. Srini","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"V.P. Srini","raw_affiliation_strings":["Media System Laboratory, Department of Computer Science, Yonsei University, College of Engineering, 134 Shinchon-Dong, Sudaemoon-Ku, Seoul, 120-749, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Media System Laboratory, Department of Computer Science, Yonsei University, College of Engineering, 134 Shinchon-Dong, Sudaemoon-Ku, Seoul, 120-749, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113392523","display_name":"Tengfei Han","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"T.-D. Han","raw_affiliation_strings":["Media System Laboratory, Department of Computer Science, Yonsei University, College of Engineering, 134 Shinchon-Dong, Sudaemoon-Ku, Seoul, 120-749, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Media System Laboratory, Department of Computer Science, Yonsei University, College of Engineering, 134 Shinchon-Dong, Sudaemoon-Ku, Seoul, 120-749, South Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2000,"currency":"EUR","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.06101176,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"1","issue":"5","first_page":"501","last_page":"507"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7434264421463013},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7272587418556213},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.622079610824585},{"id":"https://openalex.org/keywords/directx","display_name":"DirectX","score":0.6212362051010132},{"id":"https://openalex.org/keywords/opengl","display_name":"OpenGL","score":0.61083984375},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5430663228034973},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5369460582733154},{"id":"https://openalex.org/keywords/graphics-pipeline","display_name":"Graphics pipeline","score":0.5306445956230164},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.48342812061309814},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.47802743315696716},{"id":"https://openalex.org/keywords/3d-computer-graphics","display_name":"3D computer graphics","score":0.4692685008049011},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45627206563949585},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.43001434206962585},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42612335085868835},{"id":"https://openalex.org/keywords/computer-graphics","display_name":"Computer graphics (images)","score":0.31319981813430786},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1739346981048584},{"id":"https://openalex.org/keywords/visualization","display_name":"Visualization","score":0.14676973223686218}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7434264421463013},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7272587418556213},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.622079610824585},{"id":"https://openalex.org/C544400634","wikidata":"https://www.wikidata.org/wiki/Q188695","display_name":"DirectX","level":2,"score":0.6212362051010132},{"id":"https://openalex.org/C2778305236","wikidata":"https://www.wikidata.org/wiki/Q178570","display_name":"OpenGL","level":3,"score":0.61083984375},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5430663228034973},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5369460582733154},{"id":"https://openalex.org/C173552908","wikidata":"https://www.wikidata.org/wiki/Q1366289","display_name":"Graphics pipeline","level":4,"score":0.5306445956230164},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.48342812061309814},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.47802743315696716},{"id":"https://openalex.org/C66629338","wikidata":"https://www.wikidata.org/wiki/Q189177","display_name":"3D computer graphics","level":3,"score":0.4692685008049011},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45627206563949585},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.43001434206962585},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42612335085868835},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.31319981813430786},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1739346981048584},{"id":"https://openalex.org/C36464697","wikidata":"https://www.wikidata.org/wiki/Q451553","display_name":"Visualization","level":2,"score":0.14676973223686218},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/iet-cdt:20050205","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt:20050205","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers & Digital Techniques","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5799999833106995}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2063084220","https://openalex.org/W2073421970","https://openalex.org/W2086587199","https://openalex.org/W2125943663","https://openalex.org/W2136298685","https://openalex.org/W2165312212","https://openalex.org/W4239667456"],"related_works":["https://openalex.org/W2132794636","https://openalex.org/W2045602725","https://openalex.org/W2377719803","https://openalex.org/W1596594535","https://openalex.org/W633091785","https://openalex.org/W2032706116","https://openalex.org/W2369173903","https://openalex.org/W2187030146","https://openalex.org/W1598942666","https://openalex.org/W4285480322"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,58,88,115,122],"simulation":[4,17],"and":[5,18,27,47,93,121,129,138,144],"development":[6,107],"environment":[7,20,108],"for":[8,61,136],"designing":[9,87],"mobile":[10,38,89,116,140],"three-dimensional":[11],"(3D)":[12],"graphics":[13,40,91,117],"architectures.":[14],"The":[15,32,79,126],"proposed":[16,127],"verification":[19,70],"(SVE)":[21],"uses":[22],"glTrace's":[23],"ability":[24],"to":[25],"intercept":[26],"redirect":[28],"an":[29],"OpenGL|ES":[30],"streams.":[31],"SVE":[33,83,128],"simulates":[34],"the":[35,43,49,62,76,82,95,130],"behaviour":[36],"of":[37,45,81],"3D":[39,90],"pipeline":[41],"during":[42],"playback":[44],"traces":[46],"produces":[48],"second":[50],"geometry":[51],"trace":[52],"that":[53,113],"can":[54,71],"be":[55,72,133],"used":[56,135],"as":[57],"test":[59],"vector":[60],"Verilog/hardware":[63],"discription":[64],"language":[65],"RT-level":[66],"model.":[67],"An":[68,105],"architectural":[69,142],"conducted":[73],"by":[74,86],"comparing":[75],"frame-by-frame":[77],"results.":[78],"functionality":[80],"is":[84,110],"demonstrated":[85],"architecture":[92,97],"implementing":[94],"verified":[96],"on":[98],"field":[99],"programmable":[100],"gate":[101],"array":[102],"(FPGA)":[103],"boards.":[104],"application":[106,118],"(ADE)":[109],"also":[111],"presented":[112],"includes":[114],"programming":[119],"interface":[120],"device":[123],"driver":[124],"interface.":[125],"ADE":[131],"could":[132],"efficiently":[134],"developing":[137],"testing":[139],"applications,":[141],"analysis":[143],"hardware":[145],"designs.":[146]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}