{"id":"https://openalex.org/W2031678799","doi":"https://doi.org/10.1049/iet-cds:20045173","title":"Design and analysis of digital data recovery circuits using oversampling","display_name":"Design and analysis of digital data recovery circuits using oversampling","publication_year":2007,"publication_date":"2007-02-15","ids":{"openalex":"https://openalex.org/W2031678799","doi":"https://doi.org/10.1049/iet-cds:20045173","mag":"2031678799"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cds:20045173","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cds:20045173","pdf_url":null,"source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices &amp; Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061859062","display_name":"Shyh\u2010Jye Jou","orcid":"https://orcid.org/0000-0002-8821-3486"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"S.-J. Jou","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101574394","display_name":"Chia\u2010Hung Lin","orcid":"https://orcid.org/0000-0002-1819-7310"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"C.-H. Lin","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047695560","display_name":"Yu\u2010Hsin Chen","orcid":"https://orcid.org/0000-0002-9603-7371"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Y.-H. Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, Republic of China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, Republic of China","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034892114","display_name":"Zhixian Li","orcid":"https://orcid.org/0000-0002-6721-536X"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Z.-H. Li","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, Republic of China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, Republic of China","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5061859062"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":{"value":2000,"currency":"EUR","value_usd":2200},"apc_paid":null,"fwci":1.7562,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.84759912,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"1","issue":"1","first_page":"93","last_page":"101"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.9224222898483276},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.785797119140625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6868715882301331},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5067158341407776},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42476382851600647},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.41254034638404846},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.396767795085907},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3881024420261383},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.18783438205718994},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16199246048927307}],"concepts":[{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.9224222898483276},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.785797119140625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6868715882301331},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5067158341407776},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42476382851600647},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.41254034638404846},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.396767795085907},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3881024420261383},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.18783438205718994},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16199246048927307},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/iet-cds:20045173","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cds:20045173","pdf_url":null,"source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":false,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices &amp; Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.47999998927116394}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1988315752","https://openalex.org/W2056021806","https://openalex.org/W2096068274","https://openalex.org/W2103845095","https://openalex.org/W2105696031","https://openalex.org/W2112360852","https://openalex.org/W2115434507","https://openalex.org/W2116902131","https://openalex.org/W2124354408","https://openalex.org/W2124390946","https://openalex.org/W2125528240","https://openalex.org/W2131340432","https://openalex.org/W2170923463","https://openalex.org/W2171825402","https://openalex.org/W2178227197"],"related_works":["https://openalex.org/W1565428738","https://openalex.org/W2113302467","https://openalex.org/W2181640182","https://openalex.org/W2554461666","https://openalex.org/W3083817078","https://openalex.org/W1976203537","https://openalex.org/W1582443377","https://openalex.org/W2202808805","https://openalex.org/W2144347227","https://openalex.org/W2612287248"],"abstract_inverted_index":{"A":[0,97],"performance":[1],"evaluation":[2],"and":[3,21,74,132],"circuit":[4,117],"architecture":[5,17,48],"for":[6,25],"all-digital":[7,114],"data":[8,70,88,115],"recovery":[9,89,116],"using":[10],"an":[11],"oversampling":[12,75,79],"method":[13],"is":[14,18,107],"proposed.":[15],"The":[16],"very":[19,23,49],"regular":[20],"hence":[22],"suitable":[24,50],"standard-cell":[26,130],"implementation":[27,110],"flow.":[28],"Due":[29],"to":[30,60],"its":[31],"feedforward":[32],"architecture,":[33],"the":[34,46,61,65,78,103,112],"required":[35],"bit-rate":[36],"can":[37,90,101,118],"be":[38,91],"achieved":[39],"through":[40],"proper":[41],"pipelining.":[42],"These":[43],"properties":[44],"make":[45],"proposed":[47,113],"as":[51],"soft":[52],"silicon":[53],"intellectual":[54],"property.":[55],"Analysis":[56],"of":[57,64,87],"BER":[58],"due":[59],"combined":[62],"effects":[63],"key":[66],"design":[67,95,104,131],"parameters":[68,105],"like":[69],"jitter,":[71],"clock":[72],"jitter":[73],"ratio":[76],"in":[77],"technique":[80],"are":[81],"carried":[82],"out.":[83],"Thus":[84],"different":[85,94],"specifications":[86],"designed":[92],"with":[93,123],"parameters.":[96],"module":[98],"generator":[99],"that":[100],"estimate":[102],"automatically":[106],"established.":[108],"Design":[109],"shows":[111],"achieve":[119],"3.07":[120],"Gbit/s":[121],"(post-layout)":[122],"0.25":[124],"\u00b5m":[125],"2.5":[126],"V":[127],"CMOS":[128],"technology":[129],"occupies":[133],"380\u00d7390":[134],"\u00b5m2":[135],"chip":[136],"area.":[137]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
