{"id":"https://openalex.org/W7129493227","doi":"https://doi.org/10.1049/cds2/5545245","title":"An FSM\u2010Enabled Reconfigurable Debugging Approach for Area\u2010Optimized FIR Filters on FPGA Platforms","display_name":"An FSM\u2010Enabled Reconfigurable Debugging Approach for Area\u2010Optimized FIR Filters on FPGA Platforms","publication_year":2026,"publication_date":"2026-01-01","ids":{"openalex":"https://openalex.org/W7129493227","doi":"https://doi.org/10.1049/cds2/5545245"},"language":"en","primary_location":{"id":"doi:10.1049/cds2/5545245","is_oa":true,"landing_page_url":"https://doi.org/10.1049/cds2/5545245","pdf_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2/5545245","source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices & Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2/5545245","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5126258721","display_name":"Murali Anumothu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210121746","display_name":"Ministry of Electronics and Information Technology","ror":"https://ror.org/02z31cn83","country_code":"IN","type":"government","lineage":["https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Murali Anumothu","raw_affiliation_strings":["Department of Electronics and Communication Engineering ,  QIS College of Engineering and Technology ,  Ongole ,  Andhra Pradesh ,  India ,  qiscet.edu.in"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering ,  QIS College of Engineering and Technology ,  Ongole ,  Andhra Pradesh ,  India ,  qiscet.edu.in","institution_ids":["https://openalex.org/I4210121746"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5126231952","display_name":"G. M. Anitha Priyadarshini","orcid":null},"institutions":[{"id":"https://openalex.org/I4210115222","display_name":"Advanced Numerical Research and Analysis Group","ror":"https://ror.org/02a61vy29","country_code":"IN","type":"facility","lineage":["https://openalex.org/I1340206300","https://openalex.org/I4210115222","https://openalex.org/I4210150591"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"G. M. Anitha Priyadarshini","raw_affiliation_strings":["Department of Electronics and Communication Engineering ,  Anurag University ,  Hyderabad ,  India ,  anurag.edu.in"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering ,  Anurag University ,  Hyderabad ,  India ,  anurag.edu.in","institution_ids":["https://openalex.org/I4210115222"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041187342","display_name":"Ch. Hima Bindu","orcid":"https://orcid.org/0000-0002-1268-7802"},"institutions":[{"id":"https://openalex.org/I4210121746","display_name":"Ministry of Electronics and Information Technology","ror":"https://ror.org/02z31cn83","country_code":"IN","type":"government","lineage":["https://openalex.org/I4210121746"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ch. Hima Bindu","raw_affiliation_strings":["Department of Electronics and Communication Engineering ,  QIS College of Engineering and Technology ,  Ongole ,  Andhra Pradesh ,  India ,  qiscet.edu.in"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering ,  QIS College of Engineering and Technology ,  Ongole ,  Andhra Pradesh ,  India ,  qiscet.edu.in","institution_ids":["https://openalex.org/I4210121746"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059873336","display_name":"Rajanikanth Aluvalu","orcid":"https://orcid.org/0000-0001-8508-6066"},"institutions":[{"id":"https://openalex.org/I244572783","display_name":"Symbiosis International University","ror":"https://ror.org/005r2ww51","country_code":"IN","type":"education","lineage":["https://openalex.org/I244572783"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajanikanth Aluvalu","raw_affiliation_strings":["Symbiosis Institute of Technology ,  Hyderabad Campus ,  Symbiosis International (Deemed University) ,  Pune ,  India ,  sitpune.edu.in"],"raw_orcid":"https://orcid.org/0000-0001-8508-6066","affiliations":[{"raw_affiliation_string":"Symbiosis Institute of Technology ,  Hyderabad Campus ,  Symbiosis International (Deemed University) ,  Pune ,  India ,  sitpune.edu.in","institution_ids":["https://openalex.org/I244572783"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5126201643","display_name":"Sai Prashanth Mallellu","orcid":null},"institutions":[{"id":"https://openalex.org/I244572783","display_name":"Symbiosis International University","ror":"https://ror.org/005r2ww51","country_code":"IN","type":"education","lineage":["https://openalex.org/I244572783"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sai Prashanth Mallellu","raw_affiliation_strings":["Symbiosis Institute of Technology ,  Hyderabad Campus ,  Symbiosis International (Deemed University) ,  Pune ,  India ,  sitpune.edu.in"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Symbiosis Institute of Technology ,  Hyderabad Campus ,  Symbiosis International (Deemed University) ,  Pune ,  India ,  sitpune.edu.in","institution_ids":["https://openalex.org/I244572783"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Pankaj Kumar","orcid":"https://orcid.org/0000-0001-8123-3209"},"institutions":[{"id":"https://openalex.org/I164861460","display_name":"Manipal Academy of Higher Education","ror":"https://ror.org/02xzytt36","country_code":"IN","type":"education","lineage":["https://openalex.org/I164861460"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Pankaj Kumar","raw_affiliation_strings":["Manipal Institute of Technology ,  Manipal Academy of Higher Education ,  Manipal ,  India ,  manipal.edu"],"raw_orcid":"https://orcid.org/0000-0001-8123-3209","affiliations":[{"raw_affiliation_string":"Manipal Institute of Technology ,  Manipal Academy of Higher Education ,  Manipal ,  India ,  manipal.edu","institution_ids":["https://openalex.org/I164861460"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5126262820","display_name":"Ghanshyam G. Tejani","orcid":null},"institutions":[{"id":"https://openalex.org/I146367977","display_name":"Applied Science Private University","ror":"https://ror.org/01ah6nb52","country_code":"JO","type":"education","lineage":["https://openalex.org/I146367977"]},{"id":"https://openalex.org/I4210134386","display_name":"G Pulla Reddy Dental College & Hospital","ror":"https://ror.org/04p93kz40","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210134386"]}],"countries":["IN","JO"],"is_corresponding":true,"raw_author_name":"Ghanshyam G. Tejani","raw_affiliation_strings":["Applied Science Research Center ,  Applied Science Private University ,  Amman ,  11937 ,  Jordan ,  asu.edu.jo","Department of Mechanical Engineering ,  G. Pullaiah College of Engineering and Technology ,  Kurnool ,  518452 ,  Andhra Pradesh ,  India"],"raw_orcid":"https://orcid.org/0000-0001-9106-0313","affiliations":[{"raw_affiliation_string":"Applied Science Research Center ,  Applied Science Private University ,  Amman ,  11937 ,  Jordan ,  asu.edu.jo","institution_ids":["https://openalex.org/I146367977"]},{"raw_affiliation_string":"Department of Mechanical Engineering ,  G. Pullaiah College of Engineering and Technology ,  Kurnool ,  518452 ,  Andhra Pradesh ,  India","institution_ids":["https://openalex.org/I4210134386"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019996443","display_name":"Seyed Jalaleddin Mousavirad","orcid":"https://orcid.org/0000-0001-8661-7578"},"institutions":[{"id":"https://openalex.org/I56475706","display_name":"Mid Sweden University","ror":"https://ror.org/019k1pd13","country_code":"SE","type":"education","lineage":["https://openalex.org/I56475706"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Seyed Jalaleddin Mousavirad","raw_affiliation_strings":["Department of Computer and Electrical Engineering ,  Mid Sweden University ,  Sundsvall ,  Sweden ,  miun.se"],"raw_orcid":"https://orcid.org/0000-0001-8661-7578","affiliations":[{"raw_affiliation_string":"Department of Computer and Electrical Engineering ,  Mid Sweden University ,  Sundsvall ,  Sweden ,  miun.se","institution_ids":["https://openalex.org/I56475706"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5019996443","https://openalex.org/A5126262820"],"corresponding_institution_ids":["https://openalex.org/I146367977","https://openalex.org/I164861460","https://openalex.org/I4210134386","https://openalex.org/I56475706"],"apc_list":{"value":2000,"currency":"EUR","value_usd":2200},"apc_paid":{"value":2000,"currency":"EUR","value_usd":2200},"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.31675276,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2026","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.3239000141620636,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.3239000141620636,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.17919999361038208,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.08699999749660492,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8094000220298767},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7735999822616577},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.652400016784668},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.43059998750686646},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.37540000677108765},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.36070001125335693},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.3456999957561493},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.3409000039100647}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8094000220298767},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7735999822616577},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6712999939918518},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.652400016784668},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6380000114440918},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4925999939441681},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.43059998750686646},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.37540000677108765},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.36070001125335693},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.3456999957561493},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.3409000039100647},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33309999108314514},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.3012000024318695},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.2824000120162964},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.28110000491142273},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.27880001068115234},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.27559998631477356},{"id":"https://openalex.org/C72279823","wikidata":"https://www.wikidata.org/wiki/Q1139726","display_name":"Impulse response","level":2,"score":0.2702000141143799},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.2669000029563904},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2587999999523163},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.2542000114917755},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.2540999948978424},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.2526000142097473},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.25099998712539673}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1049/cds2/5545245","is_oa":true,"landing_page_url":"https://doi.org/10.1049/cds2/5545245","pdf_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2/5545245","source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices & Systems","raw_type":"journal-article"},{"id":"pmh:oai:DiVA.org:miun-56818","is_oa":true,"landing_page_url":"http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-56818","pdf_url":"https://miun.diva-portal.org/smash/get/diva2:2043569/FULLTEXT01","source":{"id":"https://openalex.org/S4306401559","display_name":"KTH Publication Database DiVA (KTH Royal Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"doi:10.1049/cds2/5545245","is_oa":true,"landing_page_url":"https://doi.org/10.1049/cds2/5545245","pdf_url":"https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2/5545245","source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":true,"is_in_doaj":true,"is_core":true,"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices & Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5152782797813416,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W7129493227.pdf","grobid_xml":"https://content.openalex.org/works/W7129493227.grobid-xml"},"referenced_works_count":16,"referenced_works":["https://openalex.org/W1971655433","https://openalex.org/W2081112821","https://openalex.org/W2092185683","https://openalex.org/W2095761111","https://openalex.org/W2103244632","https://openalex.org/W2120173944","https://openalex.org/W2127012503","https://openalex.org/W2141919235","https://openalex.org/W2162756981","https://openalex.org/W2166029537","https://openalex.org/W2343695530","https://openalex.org/W2527368021","https://openalex.org/W2808778877","https://openalex.org/W3120049971","https://openalex.org/W4255530044","https://openalex.org/W4404563188"],"related_works":[],"abstract_inverted_index":{"This":[0,110,125,142,172,203],"work":[1,111],"introduces":[2],"a":[3,17,43,62,81,139,179,227],"novel":[4],"method":[5],"to":[6,75,158],"improve":[7,217],"hardware":[8,190],"debugging":[9,39],"efficiency":[10,97,169,219],"and":[11,58,98,113,167,212,220],"decrease":[12,82],"computing":[13],"time":[14],"by":[15,41,101,120,151,183,198],"employing":[16],"finite":[18],"state":[19],"machine":[20],"(FSM)\u2010based":[21],"reconfigurable":[22,63,213],"buffer":[23,143,182,210],"insertion":[24,211],"strategy":[25,35],"for":[26,46,135,230],"optimizing":[27],"field\u2010programmable":[28],"gate":[29],"array":[30],"(FPGA)":[31],"performance.":[32],"The":[33,92,189],"proposed":[34,201],"greatly":[36],"enhances":[37],"the":[38,52,84,115,129,136,145,164,193,207],"process":[40],"offering":[42],"systematic":[44],"approach":[45,173],"error":[47],"discovery,":[48],"so":[49],"ensuring":[50],"that":[51,206],"FPGA":[53,221],"functions":[54],"with":[55,122,178],"diminished":[56],"complexity":[57,191],"increased":[59],"dependability.":[60],"Additionally,":[61],"decision":[64],"tree":[65],"generation":[66],"(DTG)\u2010finite":[67],"impulse":[68],"response":[69],"(FIR)":[70],"filter":[71,215],"design":[72,166,216],"is":[73,195],"shown":[74],"optimize":[76],"circuit":[77,194],"area,":[78],"resulting":[79],"in":[80,83,95,105,156],"quantity":[85],"of":[86,107,131,138,147,186,192],"stored":[87],"memory":[88],"look\u2010up":[89],"tables":[90],"(LUTs).":[91],"substantial":[93],"enhancement":[94],"power":[96],"area":[99,222],"attained":[100],"using":[102,199],"4":[103],"LUTs":[104],"place":[106],"6":[108],"LUTs.":[109],"executes":[112],"verifies":[114],"register\u2010transfer":[116],"level":[117],"(RTL)":[118],"functionality":[119],"operating":[121],"16":[123,148,154],"taps.":[124],"idea":[126],"depends":[127],"on":[128],"usage":[130,146,185],"an":[132],"FSM":[133],"controller":[134],"utilization":[137],"common":[140,181],"buffer.":[141],"eliminates":[144],"distinct":[149],"buffers":[150],"sharing":[152],"all":[153],"taps":[155],"order":[157],"identify":[159],"errors.":[160],"With":[161],"this":[162,200],"approach,":[163],"simplified":[165],"overall":[168],"are":[170],"improved.":[171],"achieves":[174],"improved":[175],"debug":[176],"capabilities":[177],"single":[180],"eliminating":[184],"multiple":[187],"buffers.":[188],"decreased":[196],"substantially":[197],"model.":[202],"model":[204],"proves":[205],"suggested":[208],"FSM\u2010based":[209],"FIR":[214],"computational":[218],"optimization,":[223],"positioning":[224],"it":[225],"as":[226],"viable":[228],"alternative":[229],"forthcoming":[231],"FPGA\u2010based":[232],"designs.":[233]},"counts_by_year":[],"updated_date":"2026-05-01T08:36:08.643496","created_date":"2026-02-18T00:00:00"}