{"id":"https://openalex.org/W2095971709","doi":"https://doi.org/10.1023/a:1024696110831","title":"Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors","display_name":"Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors","publication_year":2003,"publication_date":"2003-08-01","ids":{"openalex":"https://openalex.org/W2095971709","doi":"https://doi.org/10.1023/a:1024696110831","mag":"2095971709"},"language":"en","primary_location":{"id":"doi:10.1023/a:1024696110831","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1024696110831","pdf_url":null,"source":{"id":"https://openalex.org/S200807567","display_name":"Journal of Electronic Testing","issn_l":"0923-8174","issn":["0923-8174","1573-0727"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electronic Testing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075936732","display_name":"Xiao Liu","orcid":"https://orcid.org/0000-0001-8400-5754"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiao Liu","raw_affiliation_strings":["The Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA","The Bradley Dept. Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"The Bradley Dept. Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108516165","display_name":"Michael S. Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael S. Hsiao","raw_affiliation_strings":["The Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA","The Bradley Dept. Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"The Bradley Dept. Electrical & Computer Engineering, Virginia Tech, Blacksburg, VA 24061, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102184443","display_name":"Sreejit Chakravarty","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sreejit Chakravarty","raw_affiliation_strings":["Intel Architecture Group, Intel Corporation, Santa Clara, CA, 95052, USA","Intel Architecture Group, Intel Corporation, Santa Clara, CA 95052, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Architecture Group, Intel Corporation, Santa Clara, CA, 95052, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Architecture Group, Intel Corporation, Santa Clara, CA 95052, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043215850","display_name":"Paul J. Thadikaran","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul J. Thadikaran","raw_affiliation_strings":["Intel Architecture Group, Intel Corporation, Santa Clara, CA, 95052, USA","Intel Architecture Group, Intel Corporation, Santa Clara, CA 95052, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Architecture Group, Intel Corporation, Santa Clara, CA, 95052, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Architecture Group, Intel Corporation, Santa Clara, CA 95052, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2990,"currency":"USD","value_usd":2990},"apc_paid":null,"fwci":1.1514,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.80931043,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"19","issue":"4","first_page":"437","last_page":"445"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8214082717895508},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6336460709571838},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6306469440460205},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.615371823310852},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.613500714302063},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.5880278944969177},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5679855346679688},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.48470330238342285},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.47489824891090393},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.46558845043182373},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4242759346961975},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.410926878452301},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.32393503189086914},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21904876828193665},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2149602174758911},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21197211742401123},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16134437918663025}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8214082717895508},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6336460709571838},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6306469440460205},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.615371823310852},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.613500714302063},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.5880278944969177},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5679855346679688},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.48470330238342285},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.47489824891090393},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.46558845043182373},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4242759346961975},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.410926878452301},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32393503189086914},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21904876828193665},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2149602174758911},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21197211742401123},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16134437918663025},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1023/a:1024696110831","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1024696110831","pdf_url":null,"source":{"id":"https://openalex.org/S200807567","display_name":"Journal of Electronic Testing","issn_l":"0923-8174","issn":["0923-8174","1573-0727"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electronic Testing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W13277579","https://openalex.org/W1859798932","https://openalex.org/W1969474413","https://openalex.org/W2061946964","https://openalex.org/W2096110076","https://openalex.org/W2102127226","https://openalex.org/W2108103162","https://openalex.org/W2110164501","https://openalex.org/W2118744758","https://openalex.org/W2143744297","https://openalex.org/W2160010735","https://openalex.org/W2165817266","https://openalex.org/W2168755502","https://openalex.org/W3149357776","https://openalex.org/W3149518392","https://openalex.org/W6600530048"],"related_works":["https://openalex.org/W2786111245","https://openalex.org/W3009953521","https://openalex.org/W4285708951","https://openalex.org/W2021253405","https://openalex.org/W1991935474","https://openalex.org/W2091533492","https://openalex.org/W1493811107","https://openalex.org/W2408214455","https://openalex.org/W1953724919","https://openalex.org/W2128148266"],"abstract_inverted_index":null,"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2016-06-24T00:00:00"}
