{"id":"https://openalex.org/W1534252212","doi":"https://doi.org/10.1023/a:1008773308108","title":"The Formal Design of 1M-gate ASICs","display_name":"The Formal Design of 1M-gate ASICs","publication_year":2000,"publication_date":"2000-01-01","ids":{"openalex":"https://openalex.org/W1534252212","doi":"https://doi.org/10.1023/a:1008773308108","mag":"1534252212"},"language":"en","primary_location":{"id":"doi:10.1023/a:1008773308108","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008773308108","pdf_url":null,"source":{"id":"https://openalex.org/S3845260","display_name":"Formal Methods in System Design","issn_l":"0925-9856","issn":["0925-9856","1572-8102"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Formal Methods in System Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017686874","display_name":"\u00e1sgeir \u00fe\u00f3r Eir\u00edksson","orcid":null},"institutions":[{"id":"https://openalex.org/I93085520","display_name":"Silicon Labs (United States)","ror":"https://ror.org/02dyqfb80","country_code":"US","type":"company","lineage":["https://openalex.org/I93085520"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"\u00c1sgeir \u00fe\u00f3r Eir\u00edksson","raw_affiliation_strings":["Silicon Graphics Inc., Mountain View, California, USA","Silicon Graphics Inc., Mountain View, California, USA. asgeir.eiriksson@computer.org#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Graphics Inc., Mountain View, California, USA","institution_ids":["https://openalex.org/I93085520"]},{"raw_affiliation_string":"Silicon Graphics Inc., Mountain View, California, USA. asgeir.eiriksson@computer.org#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5017686874"],"corresponding_institution_ids":["https://openalex.org/I93085520"],"apc_list":{"value":3490,"currency":"USD","value_usd":3490},"apc_paid":null,"fwci":1.5701,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.84210526,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"16","issue":"1","first_page":"7","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.822558581829071},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6674978733062744},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5104855298995972},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5035006403923035},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.47821518778800964},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.46764087677001953},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4606386125087738},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.46052226424217224},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4528655409812927},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4370363652706146},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4285598695278168},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41200560331344604},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38307860493659973},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1429932415485382}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.822558581829071},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6674978733062744},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5104855298995972},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5035006403923035},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.47821518778800964},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.46764087677001953},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4606386125087738},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.46052226424217224},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4528655409812927},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4370363652706146},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4285598695278168},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41200560331344604},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38307860493659973},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1429932415485382},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1023/a:1008773308108","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008773308108","pdf_url":null,"source":{"id":"https://openalex.org/S3845260","display_name":"Formal Methods in System Design","issn_l":"0925-9856","issn":["0925-9856","1572-8102"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Formal Methods in System Design","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1500286044","https://openalex.org/W1934511824","https://openalex.org/W1986558678","https://openalex.org/W2069984295","https://openalex.org/W2100720297","https://openalex.org/W2109338287","https://openalex.org/W2110648791","https://openalex.org/W2538478261","https://openalex.org/W2542290040","https://openalex.org/W4242056968"],"related_works":["https://openalex.org/W2070693700","https://openalex.org/W2117342402","https://openalex.org/W2128735135","https://openalex.org/W2939780197","https://openalex.org/W1663661117","https://openalex.org/W2006962382","https://openalex.org/W2149716943","https://openalex.org/W2037121848","https://openalex.org/W4312733571","https://openalex.org/W113732979"],"abstract_inverted_index":null,"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2016-06-24T00:00:00"}