{"id":"https://openalex.org/W3111223568","doi":"https://doi.org/10.1023/a:1008274631859","title":"Designing \u201cDual Personality\u201d IEEE 1149.1 Compliant Multi-Chip Modules","display_name":"Designing \u201cDual Personality\u201d IEEE 1149.1 Compliant Multi-Chip Modules","publication_year":1997,"publication_date":"1997-02-01","ids":{"openalex":"https://openalex.org/W3111223568","doi":"https://doi.org/10.1023/a:1008274631859","mag":"3111223568"},"language":"en","primary_location":{"id":"doi:10.1023/a:1008274631859","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008274631859","pdf_url":null,"source":{"id":"https://openalex.org/S200807567","display_name":"Journal of Electronic Testing","issn_l":"0923-8174","issn":["0923-8174","1573-0727"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electronic Testing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028081469","display_name":"N. Jarwala","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Najmi Jarwala","raw_affiliation_strings":["Bell Labs, Engineering Research Center, Princeton, NJ, 08540"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bell Labs, Engineering Research Center, Princeton, NJ, 08540","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5028081469"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":{"value":2990,"currency":"USD","value_usd":2990},"apc_paid":null,"fwci":0.8581,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81598985,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"10","issue":"1-2","first_page":"77","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9840999841690063,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9801999926567078,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.7260353565216064},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5576439499855042},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5400318503379822},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.4936915338039398},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.48506465554237366},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.45571067929267883},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4455234110355377},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34906476736068726},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3216429054737091},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24697062373161316},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2152998447418213},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.20863470435142517},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2015908658504486},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.08414554595947266}],"concepts":[{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.7260353565216064},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5576439499855042},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5400318503379822},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.4936915338039398},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.48506465554237366},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.45571067929267883},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4455234110355377},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34906476736068726},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3216429054737091},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24697062373161316},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2152998447418213},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.20863470435142517},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2015908658504486},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.08414554595947266},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1023/a:1008274631859","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008274631859","pdf_url":null,"source":{"id":"https://openalex.org/S200807567","display_name":"Journal of Electronic Testing","issn_l":"0923-8174","issn":["0923-8174","1573-0727"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electronic Testing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2379280877","https://openalex.org/W2001654810","https://openalex.org/W2538042735","https://openalex.org/W1484535011","https://openalex.org/W2083969764","https://openalex.org/W2105797754","https://openalex.org/W2131992284","https://openalex.org/W2352722123","https://openalex.org/W2172081922","https://openalex.org/W2117171289"],"abstract_inverted_index":null,"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2020-12-21T00:00:00"}
