{"id":"https://openalex.org/W1604190567","doi":"https://doi.org/10.1023/a:1008211321698","title":"Design and Simulation of the Aquarius-II Multiprocessor","display_name":"Design and Simulation of the Aquarius-II Multiprocessor","publication_year":1997,"publication_date":"1997-08-01","ids":{"openalex":"https://openalex.org/W1604190567","doi":"https://doi.org/10.1023/a:1008211321698","mag":"1604190567"},"language":"en","primary_location":{"id":"doi:10.1023/a:1008211321698","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008211321698","pdf_url":null,"source":{"id":"https://openalex.org/S4210188115","display_name":"Journal of Systems Integration","issn_l":"0925-4676","issn":["0925-4676","1573-8787"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030671453","display_name":"Vason P. Srini","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Vason P. Srini","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108207376","display_name":"Tam M. Nguyen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tam M. Nguyen","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064403570","display_name":"Darren R. Busing","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Darren R. Busing","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108367539","display_name":"Mike J. Carlton","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mike J. Carlton","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033730625","display_name":"Bruce K. Holmer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bruce K. Holmer","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052501922","display_name":"Georges E. Smine","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Georges E. Smine","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5049056285","display_name":"Alvin M. Despain","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Alvin M. Despain","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5030671453"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07801047,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"2","first_page":"151","last_page":"178"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8073425889015198},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5889900326728821},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.5887877345085144},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.586425244808197},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.521831214427948},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5074817538261414},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.47697076201438904},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.44849395751953125},{"id":"https://openalex.org/keywords/semaphore","display_name":"Semaphore","score":0.43249356746673584},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4256194531917572},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3947959840297699},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.36619168519973755},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33516785502433777},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3293563425540924},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3041623830795288},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2030206024646759},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.19504356384277344},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.16948682069778442},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.10619956254959106}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8073425889015198},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5889900326728821},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.5887877345085144},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.586425244808197},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.521831214427948},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5074817538261414},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.47697076201438904},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.44849395751953125},{"id":"https://openalex.org/C95203288","wikidata":"https://www.wikidata.org/wiki/Q221682","display_name":"Semaphore","level":2,"score":0.43249356746673584},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4256194531917572},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3947959840297699},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.36619168519973755},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33516785502433777},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3293563425540924},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3041623830795288},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2030206024646759},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.19504356384277344},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.16948682069778442},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.10619956254959106},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1023/a:1008211321698","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008211321698","pdf_url":null,"source":{"id":"https://openalex.org/S4210188115","display_name":"Journal of Systems Integration","issn_l":"0925-4676","issn":["0925-4676","1573-8787"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Integration","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W153799646","https://openalex.org/W1480232631","https://openalex.org/W1481190717","https://openalex.org/W1523769955","https://openalex.org/W1530904454","https://openalex.org/W1555673550","https://openalex.org/W1584930493","https://openalex.org/W1769402780","https://openalex.org/W1975681120","https://openalex.org/W1986322294","https://openalex.org/W2015787715","https://openalex.org/W2021817036","https://openalex.org/W2023290961","https://openalex.org/W2037498252","https://openalex.org/W2055823027","https://openalex.org/W2067647055","https://openalex.org/W2069952017","https://openalex.org/W2075019661","https://openalex.org/W2097621668","https://openalex.org/W2114875708","https://openalex.org/W2117918782","https://openalex.org/W2134646900","https://openalex.org/W2144481293","https://openalex.org/W2294693415","https://openalex.org/W2327668599","https://openalex.org/W2579677907","https://openalex.org/W4230076379","https://openalex.org/W6628874164","https://openalex.org/W6631649356","https://openalex.org/W6667836949","https://openalex.org/W6677348501","https://openalex.org/W6679863249","https://openalex.org/W6702737797","https://openalex.org/W6732650970","https://openalex.org/W6734324503","https://openalex.org/W6741578456","https://openalex.org/W7027768633","https://openalex.org/W7047679775"],"related_works":["https://openalex.org/W2781952239","https://openalex.org/W1848192231","https://openalex.org/W254684032","https://openalex.org/W4230333905","https://openalex.org/W2339366892","https://openalex.org/W1942416056","https://openalex.org/W1797968800","https://openalex.org/W120214571","https://openalex.org/W2560368221","https://openalex.org/W2092233555"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
