{"id":"https://openalex.org/W97894690","doi":"https://doi.org/10.1023/a:1008129322583","title":"Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine","display_name":"Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine","publication_year":1999,"publication_date":"1999-09-01","ids":{"openalex":"https://openalex.org/W97894690","doi":"https://doi.org/10.1023/a:1008129322583","mag":"97894690"},"language":"en","primary_location":{"id":"doi:10.1023/a:1008129322583","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008129322583","pdf_url":null,"source":{"id":"https://openalex.org/S4210233059","display_name":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","issn_l":"0922-5773","issn":["0922-5773","1573-109X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of VLSI signal processing systems for signal, image and video technology","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108377289","display_name":"Eric Senn","orcid":null},"institutions":[{"id":"https://openalex.org/I4210135895","display_name":"Ecolab (France)","ror":"https://ror.org/03h13e556","country_code":"FR","type":"company","lineage":["https://openalex.org/I4210110810","https://openalex.org/I4210135895"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Eric Senn","raw_affiliation_strings":["Laboratoire G.I.P., DGA/Centre Technique d'Arcueil, 94114, Arcueil Cedex, France","DGA/Centre Technique d\u2018Arcueil, Laboratoire G.I.P., 94114 Arcueil Cedex, France#TAB#"],"affiliations":[{"raw_affiliation_string":"Laboratoire G.I.P., DGA/Centre Technique d'Arcueil, 94114, Arcueil Cedex, France","institution_ids":["https://openalex.org/I4210135895"]},{"raw_affiliation_string":"DGA/Centre Technique d\u2018Arcueil, Laboratoire G.I.P., 94114 Arcueil Cedex, France#TAB#","institution_ids":["https://openalex.org/I4210135895"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024071269","display_name":"Bertrand Zavidovique","orcid":null},"institutions":[{"id":"https://openalex.org/I4210113668","display_name":"Direction de la Recherche Fondamentale","ror":"https://ror.org/01yvj5k91","country_code":"FR","type":"facility","lineage":["https://openalex.org/I2738703131","https://openalex.org/I4210113668"]},{"id":"https://openalex.org/I277688954","display_name":"Universit\u00e9 Paris-Saclay","ror":"https://ror.org/03xjwb503","country_code":"FR","type":"education","lineage":["https://openalex.org/I277688954"]},{"id":"https://openalex.org/I204730241","display_name":"Universit\u00e9 Paris Cit\u00e9","ror":"https://ror.org/05f82e368","country_code":"FR","type":"education","lineage":["https://openalex.org/I204730241"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Bertrand Zavidovique","raw_affiliation_strings":["Institut d'Electronique Fondamentale, Universit\u00e9 Paris XI, 91405, Orsay Cedex, France","Institut d\u2018Electronique Fondamentale, Universit\u00e9 Paris XI, 91405 Orsay Cedex, France#TAB#"],"affiliations":[{"raw_affiliation_string":"Institut d'Electronique Fondamentale, Universit\u00e9 Paris XI, 91405, Orsay Cedex, France","institution_ids":["https://openalex.org/I277688954","https://openalex.org/I4210113668"]},{"raw_affiliation_string":"Institut d\u2018Electronique Fondamentale, Universit\u00e9 Paris XI, 91405 Orsay Cedex, France#TAB#","institution_ids":["https://openalex.org/I204730241","https://openalex.org/I277688954"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108377289"],"corresponding_institution_ids":["https://openalex.org/I4210135895"],"apc_list":null,"apc_paid":null,"fwci":0.6711,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69567367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"22","issue":"3","first_page":"197","last_page":"215"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7348483800888062},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6336132884025574},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5965003967285156},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5652992129325867},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4918489456176758},{"id":"https://openalex.org/keywords/hazard","display_name":"Hazard","score":0.4773600101470947},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.4407341778278351},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38358989357948303},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.28289794921875},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21966293454170227},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1104990541934967}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7348483800888062},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6336132884025574},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5965003967285156},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5652992129325867},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4918489456176758},{"id":"https://openalex.org/C49261128","wikidata":"https://www.wikidata.org/wiki/Q1132455","display_name":"Hazard","level":2,"score":0.4773600101470947},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.4407341778278351},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38358989357948303},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.28289794921875},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21966293454170227},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1104990541934967},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1023/a:1008129322583","is_oa":false,"landing_page_url":"https://doi.org/10.1023/a:1008129322583","pdf_url":null,"source":{"id":"https://openalex.org/S4210233059","display_name":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","issn_l":"0922-5773","issn":["0922-5773","1573-109X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of VLSI signal processing systems for signal, image and video technology","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1570043190","https://openalex.org/W1837263456","https://openalex.org/W1911504907","https://openalex.org/W2057082489","https://openalex.org/W2134829921","https://openalex.org/W2140792504","https://openalex.org/W2153364763","https://openalex.org/W2155533101","https://openalex.org/W3143840390","https://openalex.org/W4231905827","https://openalex.org/W4237268544"],"related_works":["https://openalex.org/W2122026593","https://openalex.org/W2116677773","https://openalex.org/W1588358165","https://openalex.org/W2155261584","https://openalex.org/W2582203024","https://openalex.org/W2370711413","https://openalex.org/W2375932043","https://openalex.org/W2052038519","https://openalex.org/W2584231425","https://openalex.org/W2049402143"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
