{"id":"https://openalex.org/W2020425984","doi":"https://doi.org/10.1016/s0928-4869(98)00020-2","title":"PARCIS: a robust parallel VLSI circuit simulator","display_name":"PARCIS: a robust parallel VLSI circuit simulator","publication_year":1999,"publication_date":"1999-03-01","ids":{"openalex":"https://openalex.org/W2020425984","doi":"https://doi.org/10.1016/s0928-4869(98)00020-2","mag":"2020425984"},"language":"en","primary_location":{"id":"doi:10.1016/s0928-4869(98)00020-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0928-4869(98)00020-2","pdf_url":null,"source":{"id":"https://openalex.org/S99091567","display_name":"Simulation Practice and Theory","issn_l":"0928-4869","issn":["0928-4869","1879-1433"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Simulation Practice and Theory","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051477660","display_name":"P. Linardis","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"P. Linardis","raw_affiliation_strings":["Department of Informatics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece","Department of Informatics, Aristotle University of Thessaloniki, 54006, Thessaloniki, GREECE#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Informatics, Aristotle University of Thessaloniki, 54006, Thessaloniki, GREECE#TAB#","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066340205","display_name":"Ioannis Vlahavas","orcid":"https://orcid.org/0000-0003-3477-8825"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"I. Vlahavas","raw_affiliation_strings":["Department of Informatics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece","Department of Informatics, Aristotle University of Thessaloniki, 54006, Thessaloniki, GREECE#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Department of Informatics, Aristotle University of Thessaloniki, 54006, Thessaloniki, GREECE#TAB#","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051477660"],"corresponding_institution_ids":["https://openalex.org/I21370196"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12058402,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"1","first_page":"91","last_page":"103"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.779842734336853},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7149070501327515},{"id":"https://openalex.org/keywords/transputer","display_name":"Transputer","score":0.6709606051445007},{"id":"https://openalex.org/keywords/decoupling","display_name":"Decoupling (probability)","score":0.6135411858558655},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5999304056167603},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5753265619277954},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5497206449508667},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5038871169090271},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47069597244262695},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29593682289123535},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12013766169548035},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11659407615661621},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.10007405281066895},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08721897006034851}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.779842734336853},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7149070501327515},{"id":"https://openalex.org/C2778319340","wikidata":"https://www.wikidata.org/wiki/Q776861","display_name":"Transputer","level":2,"score":0.6709606051445007},{"id":"https://openalex.org/C205606062","wikidata":"https://www.wikidata.org/wiki/Q5249645","display_name":"Decoupling (probability)","level":2,"score":0.6135411858558655},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5999304056167603},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5753265619277954},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5497206449508667},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5038871169090271},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47069597244262695},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29593682289123535},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12013766169548035},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11659407615661621},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.10007405281066895},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08721897006034851},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0928-4869(98)00020-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0928-4869(98)00020-2","pdf_url":null,"source":{"id":"https://openalex.org/S99091567","display_name":"Simulation Practice and Theory","issn_l":"0928-4869","issn":["0928-4869","1879-1433"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Simulation Practice and Theory","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W169904658","https://openalex.org/W1511374328","https://openalex.org/W1548102932","https://openalex.org/W1977822596","https://openalex.org/W1985952293","https://openalex.org/W2036597275","https://openalex.org/W2089443862","https://openalex.org/W2090963365","https://openalex.org/W2096180947","https://openalex.org/W2112369634","https://openalex.org/W2132793903","https://openalex.org/W2137444353","https://openalex.org/W2139030761","https://openalex.org/W2141678676","https://openalex.org/W2142580633","https://openalex.org/W2145510606","https://openalex.org/W2151480989","https://openalex.org/W2161067786","https://openalex.org/W2478091498","https://openalex.org/W2526734274","https://openalex.org/W4242609991","https://openalex.org/W4285719527","https://openalex.org/W6680641309"],"related_works":["https://openalex.org/W105768848","https://openalex.org/W2071148424","https://openalex.org/W2797868626","https://openalex.org/W142407627","https://openalex.org/W1931008194","https://openalex.org/W2215847653","https://openalex.org/W599784109","https://openalex.org/W366366381","https://openalex.org/W2155007862","https://openalex.org/W4251509818"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
