{"id":"https://openalex.org/W2586378910","doi":"https://doi.org/10.1016/j.future.2017.02.012","title":"Accurately modeling the on-chip and off-chip GPU memory subsystem","display_name":"Accurately modeling the on-chip and off-chip GPU memory subsystem","publication_year":2017,"publication_date":"2017-02-09","ids":{"openalex":"https://openalex.org/W2586378910","doi":"https://doi.org/10.1016/j.future.2017.02.012","mag":"2586378910"},"language":"en","primary_location":{"id":"doi:10.1016/j.future.2017.02.012","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.future.2017.02.012","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0167739X17302091","source":{"id":"https://openalex.org/S186357190","display_name":"Future Generation Computer Systems","issn_l":"0167-739X","issn":["0167-739X","1872-7115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Future Generation Computer Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://www.sciencedirect.com/science/article/pii/S0167739X17302091","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020902057","display_name":"Francisco Candel","orcid":"https://orcid.org/0000-0001-9458-2889"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Francisco Candel","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Salvador Petit","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain"],"raw_orcid":"https://orcid.org/0000-0003-2426-4134","affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 Duato","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, 46012 Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5020902057"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":{"value":3340,"currency":"USD","value_usd":3340},"apc_paid":null,"fwci":2.4608,"has_fulltext":true,"cited_by_count":16,"citation_normalized_percentile":{"value":0.90302009,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"82","issue":null,"first_page":"510","last_page":"519"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9012042284011841},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.7697752714157104},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6312012076377869},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5949907302856445},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5176406502723694},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5047003030776978},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.492787629365921},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4795655608177185},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4732426106929779},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4675644338130951},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4526502788066864},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.4504642188549042},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4414733648300171},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4189903438091278},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.39831045269966125},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23768478631973267},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.16796502470970154},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.10888025164604187},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.10207712650299072}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9012042284011841},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.7697752714157104},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6312012076377869},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5949907302856445},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5176406502723694},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5047003030776978},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.492787629365921},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4795655608177185},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4732426106929779},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4675644338130951},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4526502788066864},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.4504642188549042},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4414733648300171},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4189903438091278},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.39831045269966125},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23768478631973267},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.16796502470970154},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.10888025164604187},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.10207712650299072}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/j.future.2017.02.012","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.future.2017.02.012","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0167739X17302091","source":{"id":"https://openalex.org/S186357190","display_name":"Future Generation Computer Systems","issn_l":"0167-739X","issn":["0167-739X","1872-7115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Future Generation Computer Systems","raw_type":"journal-article"},{"id":"pmh:oai:riunet.upv.es:10251/145974","is_oa":true,"landing_page_url":"http://hdl.handle.net/10251/145974","pdf_url":null,"source":{"id":"https://openalex.org/S4306401646","display_name":"Repositorio Institucional de la Universitat Polit\u00e8cnica (Universitat Polit\u00e8cnica de Val\u00e8ncia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I60053951","host_organization_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","host_organization_lineage":["https://openalex.org/I60053951"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.1016/j.future.2017.02.012","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.future.2017.02.012","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0167739X17302091","source":{"id":"https://openalex.org/S186357190","display_name":"Future Generation Computer Systems","issn_l":"0167-739X","issn":["0167-739X","1872-7115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Future Generation Computer Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.49000000953674316,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G302270494","display_name":null,"funder_award_id":"TIN2012-38341-C04","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"},{"id":"https://openalex.org/G5150840395","display_name":null,"funder_award_id":"AICO/2016/059","funder_id":"https://openalex.org/F4320321864","funder_display_name":"Generalitat Valenciana"},{"id":"https://openalex.org/G8521584686","display_name":null,"funder_award_id":"TIN2012-38341-C04-01","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"}],"funders":[{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"},{"id":"https://openalex.org/F4320321864","display_name":"Generalitat Valenciana","ror":"https://ror.org/0097mvx21"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2586378910.pdf","grobid_xml":"https://content.openalex.org/works/W2586378910.grobid-xml"},"referenced_works_count":32,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1550898840","https://openalex.org/W1552720876","https://openalex.org/W1906046253","https://openalex.org/W1966668827","https://openalex.org/W1979527452","https://openalex.org/W1981124332","https://openalex.org/W1984222112","https://openalex.org/W2033486618","https://openalex.org/W2067441262","https://openalex.org/W2093043622","https://openalex.org/W2100893446","https://openalex.org/W2103742924","https://openalex.org/W2103884786","https://openalex.org/W2111734760","https://openalex.org/W2116361585","https://openalex.org/W2126256127","https://openalex.org/W2147657366","https://openalex.org/W2151195685","https://openalex.org/W2160428323","https://openalex.org/W2162639668","https://openalex.org/W2165284728","https://openalex.org/W2169880332","https://openalex.org/W2170382128","https://openalex.org/W2176864362","https://openalex.org/W2341385739","https://openalex.org/W2399715892","https://openalex.org/W2913176614","https://openalex.org/W2999610704","https://openalex.org/W4234833047","https://openalex.org/W6674989430","https://openalex.org/W6684550695"],"related_works":["https://openalex.org/W2149371164","https://openalex.org/W3108993429","https://openalex.org/W2007929622","https://openalex.org/W2606565524","https://openalex.org/W2998091606","https://openalex.org/W1982632559","https://openalex.org/W1531802798","https://openalex.org/W2782503170","https://openalex.org/W2047684617","https://openalex.org/W2586378910"],"abstract_inverted_index":null,"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}