{"id":"https://openalex.org/W1990054376","doi":"https://doi.org/10.1016/0165-6074(93)90196-r","title":"A design methodology for the correct specification of VLSI systems","display_name":"A design methodology for the correct specification of VLSI systems","publication_year":1993,"publication_date":"1993-09-01","ids":{"openalex":"https://openalex.org/W1990054376","doi":"https://doi.org/10.1016/0165-6074(93)90196-r","mag":"1990054376"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(93)90196-r","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(93)90196-r","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014159983","display_name":"Cristiana Bolchini","orcid":"https://orcid.org/0000-0001-5065-7906"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"C. Bolchini","raw_affiliation_strings":["POLITECNICO di MILANO, Dip. Electtronica, P.za Leonardo da Vinci 32, 20133 Milano, Italy"],"affiliations":[{"raw_affiliation_string":"POLITECNICO di MILANO, Dip. Electtronica, P.za Leonardo da Vinci 32, 20133 Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052422346","display_name":"M. Bombana","orcid":null},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Bombana","raw_affiliation_strings":["ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy","institution_ids":["https://openalex.org/I2799464224"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000272580","display_name":"P. Cavalloro","orcid":null},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Cavalloro","raw_affiliation_strings":["ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy","institution_ids":["https://openalex.org/I2799464224"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110454259","display_name":"C. Costi","orcid":null},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"C. Costi","raw_affiliation_strings":["ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy","institution_ids":["https://openalex.org/I2799464224"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040302302","display_name":"Franco Fummi","orcid":"https://orcid.org/0000-0002-4404-5791"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Fummi","raw_affiliation_strings":["POLITECNICO di MILANO, Dip. Electtronica, P.za Leonardo da Vinci 32, 20133 Milano, Italy"],"affiliations":[{"raw_affiliation_string":"POLITECNICO di MILANO, Dip. Electtronica, P.za Leonardo da Vinci 32, 20133 Milano, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066452434","display_name":"G. Zaza","orcid":null},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Zaza","raw_affiliation_strings":["ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy"],"affiliations":[{"raw_affiliation_string":"ITALTEL SIT, DRSC-SM, 20019 Settimo Milanese, Milano, Italy","institution_ids":["https://openalex.org/I2799464224"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5014159983"],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":null,"apc_paid":null,"fwci":1.1626,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.81264501,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"38","issue":"1-5","first_page":"563","last_page":"570"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8791258931159973},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8368827700614929},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7249088883399963},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6030096411705017},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5692183375358582},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5510901212692261},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.508202314376831},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.43928593397140503},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4326295852661133},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3484143018722534},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3048052191734314},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.23234128952026367}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8791258931159973},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8368827700614929},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7249088883399963},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6030096411705017},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5692183375358582},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5510901212692261},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.508202314376831},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.43928593397140503},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4326295852661133},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3484143018722534},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3048052191734314},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.23234128952026367}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0165-6074(93)90196-r","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(93)90196-r","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/653936","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/653936","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5299999713897705}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2088903792","https://openalex.org/W2129873456","https://openalex.org/W2131890947","https://openalex.org/W2142384583","https://openalex.org/W2152691384","https://openalex.org/W2163087258","https://openalex.org/W4234318587","https://openalex.org/W4252729222","https://openalex.org/W6672734890","https://openalex.org/W6681084769"],"related_works":["https://openalex.org/W2366556084","https://openalex.org/W1988777083","https://openalex.org/W1555025092","https://openalex.org/W2542547697","https://openalex.org/W2607447167","https://openalex.org/W2100322987","https://openalex.org/W4236604936","https://openalex.org/W1498721867","https://openalex.org/W2108827571","https://openalex.org/W2183741735"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
