{"id":"https://openalex.org/W2009358019","doi":"https://doi.org/10.1016/0165-6074(86)90095-5","title":"A VLSI architecture for the Central Processor of a digital switch","display_name":"A VLSI architecture for the Central Processor of a digital switch","publication_year":1986,"publication_date":"1986-12-01","ids":{"openalex":"https://openalex.org/W2009358019","doi":"https://doi.org/10.1016/0165-6074(86)90095-5","mag":"2009358019"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(86)90095-5","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(86)90095-5","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109248319","display_name":"P. Dasiewicz","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"P. Dasiewicz","raw_affiliation_strings":["Department of Electrical Engineering University of Waterloo Waterloo, Ontario, Canada. N2L 3G1 ph. (519) 885-1211, ext. 2866 Telex 069-55259"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering University of Waterloo Waterloo, Ontario, Canada. N2L 3G1 ph. (519) 885-1211, ext. 2866 Telex 069-55259","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037258750","display_name":"Peter Corbett","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"P.F. Corbett","raw_affiliation_strings":["Department of Electrical Engineering University of Waterloo Waterloo, Ontario, Canada. N2L 3G1 ph. (519) 885-1211, ext. 2866 Telex 069-55259"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering University of Waterloo Waterloo, Ontario, Canada. N2L 3G1 ph. (519) 885-1211, ext. 2866 Telex 069-55259","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002786982","display_name":"R.E. Seviora","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"R.E. Seviora","raw_affiliation_strings":["Department of Electrical Engineering University of Waterloo Waterloo, Ontario, Canada. N2L 3G1 ph. (519) 885-1211, ext. 2866 Telex 069-55259"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering University of Waterloo Waterloo, Ontario, Canada. N2L 3G1 ph. (519) 885-1211, ext. 2866 Telex 069-55259","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16500786,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":"1-5","first_page":"591","last_page":"595"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9096383452415466},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6756945848464966},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5095493793487549},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5029527544975281},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4932793974876404},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.491224467754364},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48598894476890564},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4617280066013336},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43613535165786743},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.41471758484840393},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40977218747138977},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.1686520278453827},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13603445887565613}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9096383452415466},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6756945848464966},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5095493793487549},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5029527544975281},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4932793974876404},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.491224467754364},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48598894476890564},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4617280066013336},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43613535165786743},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.41471758484840393},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40977218747138977},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.1686520278453827},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13603445887565613},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(86)90095-5","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(86)90095-5","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2160175950","https://openalex.org/W2294693415"],"related_works":["https://openalex.org/W2005635288","https://openalex.org/W630117873","https://openalex.org/W2098218272","https://openalex.org/W2540018280","https://openalex.org/W2141799201","https://openalex.org/W2111412181","https://openalex.org/W2101005180","https://openalex.org/W4251089459","https://openalex.org/W2102384429","https://openalex.org/W2115138121"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
