{"id":"https://openalex.org/W2047345373","doi":"https://doi.org/10.1016/s1383-7621(98)00052-6","title":"STATS: A framework for microprocessor and system-level design space exploration","display_name":"STATS: A framework for microprocessor and system-level design space exploration","publication_year":1999,"publication_date":"1999-06-01","ids":{"openalex":"https://openalex.org/W2047345373","doi":"https://doi.org/10.1016/s1383-7621(98)00052-6","mag":"2047345373"},"language":"en","primary_location":{"id":"doi:10.1016/s1383-7621(98)00052-6","is_oa":true,"landing_page_url":"https://doi.org/10.1016/s1383-7621(98)00052-6","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1016/s1383-7621(98)00052-6","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009386140","display_name":"David H. Albonesi","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"David H. Albonesi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA","Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY \u2013 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY \u2013 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055210733","display_name":"Israel Koren","orcid":"https://orcid.org/0000-0003-2741-7108"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Israel Koren","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA","institution_ids":["https://openalex.org/I24603500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5009386140"],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":{"value":2800,"currency":"USD","value_usd":2800},"apc_paid":{"value":2800,"currency":"USD","value_usd":2800},"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.13944999,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"45","issue":"12-13","first_page":"1097","last_page":"1110"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8395283222198486},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7803130149841309},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6643542051315308},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6281176209449768},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5928528308868408},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5913487672805786},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5612340569496155},{"id":"https://openalex.org/keywords/emphasis","display_name":"Emphasis (telecommunications)","score":0.5199624300003052},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4952062666416168},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.45730382204055786},{"id":"https://openalex.org/keywords/space","display_name":"Space (punctuation)","score":0.44692134857177734},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.43857714533805847},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42840060591697693},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40393832325935364},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.16998514533042908},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1635916531085968},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07552096247673035}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8395283222198486},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7803130149841309},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6643542051315308},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6281176209449768},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5928528308868408},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5913487672805786},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5612340569496155},{"id":"https://openalex.org/C177454536","wikidata":"https://www.wikidata.org/wiki/Q578290","display_name":"Emphasis (telecommunications)","level":2,"score":0.5199624300003052},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4952062666416168},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.45730382204055786},{"id":"https://openalex.org/C2778572836","wikidata":"https://www.wikidata.org/wiki/Q380933","display_name":"Space (punctuation)","level":2,"score":0.44692134857177734},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.43857714533805847},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42840060591697693},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40393832325935364},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.16998514533042908},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1635916531085968},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07552096247673035},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1016/s1383-7621(98)00052-6","is_oa":true,"landing_page_url":"https://doi.org/10.1016/s1383-7621(98)00052-6","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},{"id":"pmh:oai:scholarworks.umass.edu:ece_faculty_pubs-1790","is_oa":false,"landing_page_url":"https://scholarworks.umass.edu/ece_faculty_pubs/791","pdf_url":null,"source":{"id":"https://openalex.org/S4306402057","display_name":"Scholarworks (University of Massachusetts Amherst)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I24603500","host_organization_name":"University of Massachusetts Amherst","host_organization_lineage":["https://openalex.org/I24603500"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Electrical and Computer Engineering Faculty Publication Series","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.30.5581","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.30.5581","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.rochester.edu:8080/users/albonesi/research/papers/jsa99.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.352.6247","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.352.6247","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://euler.ecs.umass.edu/research/ak-JSA-1999.pdf","raw_type":"text"},{"id":"pmh:oai:scholarworks.umass.edu:20.500.14394/21491","is_oa":false,"landing_page_url":"https://hdl.handle.net/20.500.14394/21491","pdf_url":null,"source":{"id":"https://openalex.org/S4306402057","display_name":"Scholarworks (University of Massachusetts Amherst)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I24603500","host_organization_name":"University of Massachusetts Amherst","host_organization_lineage":["https://openalex.org/I24603500"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"published","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1016/s1383-7621(98)00052-6","is_oa":true,"landing_page_url":"https://doi.org/10.1016/s1383-7621(98)00052-6","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W72785707","https://openalex.org/W114262787","https://openalex.org/W1555017046","https://openalex.org/W1562342676","https://openalex.org/W1997641735","https://openalex.org/W2000547159","https://openalex.org/W2038198320","https://openalex.org/W2049507596","https://openalex.org/W2071053528","https://openalex.org/W2077615298","https://openalex.org/W2079159481","https://openalex.org/W2084451631","https://openalex.org/W2088141324","https://openalex.org/W2097872138","https://openalex.org/W2098722245","https://openalex.org/W2100761285","https://openalex.org/W2112379448","https://openalex.org/W2132960876","https://openalex.org/W2135324929","https://openalex.org/W2136698618","https://openalex.org/W2149340522","https://openalex.org/W2150107136","https://openalex.org/W2155861433","https://openalex.org/W3003304272","https://openalex.org/W3007374139","https://openalex.org/W4229792040","https://openalex.org/W4233431330","https://openalex.org/W4238583356","https://openalex.org/W4250823903","https://openalex.org/W4251779799","https://openalex.org/W4252905491"],"related_works":["https://openalex.org/W4230093848","https://openalex.org/W4236020707","https://openalex.org/W2133355743","https://openalex.org/W2011825025","https://openalex.org/W2117325689","https://openalex.org/W4247641071","https://openalex.org/W2120739641","https://openalex.org/W2122155038","https://openalex.org/W2124364081","https://openalex.org/W3044248149"],"abstract_inverted_index":{"As":[0],"microprocessor-based":[1,47],"systems":[2,31],"grow":[3],"in":[4,24,86],"complexity,":[5],"and":[6,49,56,65,69,79],"the":[7,28,38,54,74,77,95,106],"processor-memory":[8],"speed":[9],"gap":[10],"widens":[11],"further,":[12],"more":[13],"emphasis":[14],"needs":[15],"to":[16,26],"be":[17,84],"placed":[18],"on":[19],"early":[20,87],"design":[21,88],"space":[22,89],"exploration":[23],"order":[25],"produce":[27],"highest":[29],"performance":[30],"with":[32,42],"minimal":[33],"schedule":[34],"impact.":[35],"We":[36,72],"discuss":[37,73],"critical":[39],"issues":[40],"associated":[41],"architectural":[43,68,102],"evaluation":[44,58],"of":[45,59,76,94],"complex":[46],"systems,":[48],"present":[50],"a":[51],"methodology":[52,96],"for":[53],"comprehensive":[55],"semiautomatic":[57],"processor,":[60],"cache":[61],"hierarchy,":[62],"system":[63],"interconnect,":[64],"main":[66],"memory":[67],"technological":[70],"alternatives.":[71],"implementation":[75],"methodology,":[78],"describe":[80],"how":[81],"it":[82],"can":[83],"used":[85],"exploration.":[90],"The":[91],"unique":[92],"aspects":[93],"are":[97],"further":[98],"illustrated":[99],"through":[100],"two":[101],"investigations":[103],"performed":[104],"using":[105],"toolset.":[107]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}