{"id":"https://openalex.org/W2094179385","doi":"https://doi.org/10.1016/s1383-7621(97)00020-9","title":"An algorithm for clock cycle selection in behavioral synthesis","display_name":"An algorithm for clock cycle selection in behavioral synthesis","publication_year":1998,"publication_date":"1998-06-01","ids":{"openalex":"https://openalex.org/W2094179385","doi":"https://doi.org/10.1016/s1383-7621(97)00020-9","mag":"2094179385"},"language":"en","primary_location":{"id":"doi:10.1016/s1383-7621(97)00020-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(97)00020-9","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075045206","display_name":"P. Tabuenca","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pedro Tabuenca","raw_affiliation_strings":["Robert Bosch Espa\u00f1a, Department K8/PNK3, Hnos Garc\u00eda Noblejas, 19. Madrid 28037, Spain"],"affiliations":[{"raw_affiliation_string":"Robert Bosch Espa\u00f1a, Department K8/PNK3, Hnos Garc\u00eda Noblejas, 19. Madrid 28037, Spain","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101992779","display_name":"Pablo S\u00e1nchez","orcid":"https://orcid.org/0000-0001-7363-5814"},"institutions":[{"id":"https://openalex.org/I13134134","display_name":"Universidad de Cantabria","ror":"https://ror.org/046ffzj20","country_code":"ES","type":"education","lineage":["https://openalex.org/I13134134"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pablo S\u00e1nchez","raw_affiliation_strings":["Microelectronic Engineering Group, University of Cantabria, Avda. de los Castros, s/n. 39005 Santander, Spain"],"affiliations":[{"raw_affiliation_string":"Microelectronic Engineering Group, University of Cantabria, Avda. de los Castros, s/n. 39005 Santander, Spain","institution_ids":["https://openalex.org/I13134134"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032788928","display_name":"Eugenio Villar","orcid":"https://orcid.org/0000-0002-6541-6176"},"institutions":[{"id":"https://openalex.org/I13134134","display_name":"Universidad de Cantabria","ror":"https://ror.org/046ffzj20","country_code":"ES","type":"education","lineage":["https://openalex.org/I13134134"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Eugenio Villar","raw_affiliation_strings":["Microelectronic Engineering Group, University of Cantabria, Avda. de los Castros, s/n. 39005 Santander, Spain"],"affiliations":[{"raw_affiliation_string":"Microelectronic Engineering Group, University of Cantabria, Avda. de los Castros, s/n. 39005 Santander, Spain","institution_ids":["https://openalex.org/I13134134"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5032788928"],"corresponding_institution_ids":["https://openalex.org/I13134134"],"apc_list":{"value":2800,"currency":"USD","value_usd":2800},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17716034,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"44","issue":"9-10","first_page":"773","last_page":"786"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9865999817848206,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8243653774261475},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7493414282798767},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5922868847846985},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5568637251853943},{"id":"https://openalex.org/keywords/selection","display_name":"Selection (genetic algorithm)","score":0.4987361431121826},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.48950397968292236},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4754043519496918},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4742297828197479},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4663298428058624},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4633619785308838},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.381082147359848},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3529410660266876},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.32891035079956055},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26711851358413696},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.18205499649047852},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08225122094154358},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0713571310043335},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.05711451172828674}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8243653774261475},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7493414282798767},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5922868847846985},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5568637251853943},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.4987361431121826},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.48950397968292236},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4754043519496918},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4742297828197479},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4663298428058624},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4633619785308838},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.381082147359848},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3529410660266876},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.32891035079956055},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26711851358413696},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.18205499649047852},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08225122094154358},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0713571310043335},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.05711451172828674},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s1383-7621(97)00020-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(97)00020-9","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1963847471","https://openalex.org/W2138580694","https://openalex.org/W2162109720","https://openalex.org/W6638613300","https://openalex.org/W6663471695","https://openalex.org/W6684003967"],"related_works":["https://openalex.org/W4247089581","https://openalex.org/W2003180247","https://openalex.org/W1487986186","https://openalex.org/W331180034","https://openalex.org/W2158864330","https://openalex.org/W2520965597","https://openalex.org/W2125985608","https://openalex.org/W2378549260","https://openalex.org/W1989324326","https://openalex.org/W106389774"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}