{"id":"https://openalex.org/W1969828050","doi":"https://doi.org/10.1016/s1383-7621(03)00042-0","title":"Multiple-path execution for chip multiprocessors","display_name":"Multiple-path execution for chip multiprocessors","publication_year":2003,"publication_date":"2003-05-19","ids":{"openalex":"https://openalex.org/W1969828050","doi":"https://doi.org/10.1016/s1383-7621(03)00042-0","mag":"1969828050"},"language":"en","primary_location":{"id":"doi:10.1016/s1383-7621(03)00042-0","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(03)00042-0","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047992176","display_name":"Matthew C. Chidester","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Matthew C. Chidester","raw_affiliation_strings":["High-performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL 32611-6200, USA","High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"High-performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL 32611-6200, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082898376","display_name":"Alan D. George","orcid":"https://orcid.org/0000-0001-9665-2879"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alan D. George","raw_affiliation_strings":["High-performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL 32611-6200, USA","High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"High-performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL 32611-6200, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062286523","display_name":"Matthew Radlinski","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew A. Radlinski","raw_affiliation_strings":["High-performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL 32611-6200, USA","High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"High-performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL 32611-6200, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"High-Performance Computing and Simulation (HCS) Research Laboratory, Department of Electrical and Computer Engineering, University of Florida, 216 Larsen Hall, P.O. Box 116200, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5047992176","https://openalex.org/A5082898376"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":{"value":2800,"currency":"USD","value_usd":2800},"apc_paid":null,"fwci":0.2473,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.53085266,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"49","issue":"1-2","first_page":"33","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9160559177398682},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8492563962936401},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7613019943237305},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6153413653373718},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.5314936637878418},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5287083387374878},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5197122097015381},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45074066519737244},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.44743484258651733},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4283389449119568},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.41096359491348267},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3794668912887573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30204880237579346},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18169698119163513},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10949620604515076},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.10787853598594666}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9160559177398682},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8492563962936401},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7613019943237305},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6153413653373718},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.5314936637878418},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5287083387374878},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5197122097015381},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45074066519737244},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.44743484258651733},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4283389449119568},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.41096359491348267},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3794668912887573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30204880237579346},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18169698119163513},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10949620604515076},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.10787853598594666},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/s1383-7621(03)00042-0","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(03)00042-0","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.94.6053","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.94.6053","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.hcs.ufl.edu/pubs/MPE2003.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306078","display_name":"U.S. Department of Defense","ror":"https://ror.org/0447fe631"},{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W152254645","https://openalex.org/W1498870995","https://openalex.org/W1593372552","https://openalex.org/W1971851724","https://openalex.org/W1985063830","https://openalex.org/W2013863826","https://openalex.org/W2018069366","https://openalex.org/W2032094184","https://openalex.org/W2036162899","https://openalex.org/W2036735247","https://openalex.org/W2044062670","https://openalex.org/W2074867256","https://openalex.org/W2089319323","https://openalex.org/W2093396203","https://openalex.org/W2095667776","https://openalex.org/W2103982793","https://openalex.org/W2112833506","https://openalex.org/W2128731376","https://openalex.org/W2129523505","https://openalex.org/W2129889140","https://openalex.org/W2131867938","https://openalex.org/W2132148829","https://openalex.org/W2153948266","https://openalex.org/W2159617380","https://openalex.org/W2160401437","https://openalex.org/W2160730704","https://openalex.org/W2165423885","https://openalex.org/W2170158556","https://openalex.org/W2170585292","https://openalex.org/W2170653240","https://openalex.org/W2611703827","https://openalex.org/W4231361442","https://openalex.org/W4233399214","https://openalex.org/W4236595536","https://openalex.org/W4236787594","https://openalex.org/W4245407809","https://openalex.org/W4246403730","https://openalex.org/W4248248450","https://openalex.org/W4253172818"],"related_works":["https://openalex.org/W1539320959","https://openalex.org/W4376647684","https://openalex.org/W2027935151","https://openalex.org/W3081116756","https://openalex.org/W4221139464","https://openalex.org/W2533681803","https://openalex.org/W2055341571","https://openalex.org/W2611592534","https://openalex.org/W2364343982","https://openalex.org/W2101536355"],"abstract_inverted_index":null,"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}