{"id":"https://openalex.org/W2033062187","doi":"https://doi.org/10.1016/s1383-7621(00)00030-8","title":"An on-chip cache compression technique to reduce decompression overhead and design complexity","display_name":"An on-chip cache compression technique to reduce decompression overhead and design complexity","publication_year":2000,"publication_date":"2000-12-01","ids":{"openalex":"https://openalex.org/W2033062187","doi":"https://doi.org/10.1016/s1383-7621(00)00030-8","mag":"2033062187"},"language":"en","primary_location":{"id":"doi:10.1016/s1383-7621(00)00030-8","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(00)00030-8","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079507878","display_name":"Jang\u2010Soo Lee","orcid":"https://orcid.org/0000-0002-0255-1629"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jang-Soo Lee","raw_affiliation_strings":["Department of Computer Science, Parallel Processing System Laboratory, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Parallel Processing System Laboratory, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025409379","display_name":"Won\u2010Kee Hong","orcid":"https://orcid.org/0000-0002-1955-9598"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Won-Kee Hong","raw_affiliation_strings":["Department of Computer Science, Parallel Processing System Laboratory, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Parallel Processing System Laboratory, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032646530","display_name":"Shin\u2010Dug Kim","orcid":"https://orcid.org/0000-0002-2642-6662"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Shin-Dug Kim","raw_affiliation_strings":["Department of Computer Science, Parallel Processing System Laboratory, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Parallel Processing System Laboratory, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, South Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5032646530"],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":{"value":2800,"currency":"USD","value_usd":2800},"apc_paid":null,"fwci":0.3137,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.6380666,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"46","issue":"15","first_page":"1365","last_page":"1382"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8894410133361816},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6632202863693237},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6485635042190552},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5879812240600586},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5831982493400574},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5742353200912476},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.5717897415161133},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5004396438598633},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.4891124367713928},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.48798149824142456},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.47856977581977844},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45005157589912415},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.44081079959869385},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.4330022931098938},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.42885535955429077},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4207853078842163},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.42053475975990295},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4164232611656189},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.35962390899658203},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30464035272598267},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.284040242433548},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1773260533809662}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8894410133361816},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6632202863693237},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6485635042190552},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5879812240600586},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5831982493400574},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5742353200912476},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.5717897415161133},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5004396438598633},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.4891124367713928},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.48798149824142456},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.47856977581977844},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45005157589912415},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.44081079959869385},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.4330022931098938},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.42885535955429077},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4207853078842163},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.42053475975990295},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4164232611656189},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.35962390899658203},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30464035272598267},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.284040242433548},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1773260533809662}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s1383-7621(00)00030-8","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(00)00030-8","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W187057365","https://openalex.org/W1555915743","https://openalex.org/W1566207910","https://openalex.org/W2018761720","https://openalex.org/W2020505483","https://openalex.org/W2057627091","https://openalex.org/W2080379046","https://openalex.org/W2083269033","https://openalex.org/W2098392676","https://openalex.org/W2099961767","https://openalex.org/W2100466074","https://openalex.org/W2100913437","https://openalex.org/W2107745473","https://openalex.org/W2120459733","https://openalex.org/W2148356835","https://openalex.org/W2150073849","https://openalex.org/W2156923685","https://openalex.org/W2162164368","https://openalex.org/W2163935347","https://openalex.org/W3003597364","https://openalex.org/W4240982339","https://openalex.org/W4254073276","https://openalex.org/W4255408358","https://openalex.org/W6632847020","https://openalex.org/W6674775192"],"related_works":["https://openalex.org/W4321458411","https://openalex.org/W2782503170","https://openalex.org/W3108993429","https://openalex.org/W2047684617","https://openalex.org/W4317815260","https://openalex.org/W2041174925","https://openalex.org/W2168550483","https://openalex.org/W4233816696","https://openalex.org/W4281924108","https://openalex.org/W4382407528"],"abstract_inverted_index":null,"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}