{"id":"https://openalex.org/W2089442786","doi":"https://doi.org/10.1016/s1383-7621(00)00027-8","title":"ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs","display_name":"ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs","publication_year":2000,"publication_date":"2000-12-01","ids":{"openalex":"https://openalex.org/W2089442786","doi":"https://doi.org/10.1016/s1383-7621(00)00027-8","mag":"2089442786"},"language":"en","primary_location":{"id":"doi:10.1016/s1383-7621(00)00027-8","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(00)00027-8","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103354042","display_name":"Wolfgang G\u00fcnther","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Wolfgang G\u00fcnther","raw_affiliation_strings":["Institute of Computer Science, Chair of Computer Architecture (Prof. Dr. Bernd Becker), Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, Chair of Computer Architecture (Prof. Dr. Bernd Becker), Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["Institute of Computer Science, Chair of Computer Architecture (Prof. Dr. Bernd Becker), Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, Chair of Computer Architecture (Prof. Dr. Bernd Becker), Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103354042"],"corresponding_institution_ids":[],"apc_list":{"value":2800,"currency":"USD","value_usd":2800},"apc_paid":null,"fwci":0.6274,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.73404255,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"46","issue":"14","first_page":"1321","last_page":"1334"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9772858023643494},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8285545110702515},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7218919992446899},{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.6197717785835266},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5531588196754456},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.5521572232246399},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5113932490348816},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.49124735593795776},{"id":"https://openalex.org/keywords/greedy-algorithm","display_name":"Greedy algorithm","score":0.4875714182853699},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4586472809314728},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4207971692085266},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.41715091466903687},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3640362620353699},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35930007696151733},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2688848376274109},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.2204979658126831},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.09700140357017517},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09605073928833008},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0847594141960144}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9772858023643494},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8285545110702515},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7218919992446899},{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.6197717785835266},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5531588196754456},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.5521572232246399},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5113932490348816},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.49124735593795776},{"id":"https://openalex.org/C51823790","wikidata":"https://www.wikidata.org/wiki/Q504353","display_name":"Greedy algorithm","level":2,"score":0.4875714182853699},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4586472809314728},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4207971692085266},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.41715091466903687},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3640362620353699},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35930007696151733},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2688848376274109},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.2204979658126831},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.09700140357017517},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09605073928833008},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0847594141960144},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s1383-7621(00)00027-8","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s1383-7621(00)00027-8","pdf_url":null,"source":{"id":"https://openalex.org/S127660348","display_name":"Journal of Systems Architecture","issn_l":"1383-7621","issn":["1383-7621","1873-6165"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems Architecture","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W1500238730","https://openalex.org/W1505590927","https://openalex.org/W1511688816","https://openalex.org/W1944291514","https://openalex.org/W1979265266","https://openalex.org/W1992006970","https://openalex.org/W1995135231","https://openalex.org/W2000787196","https://openalex.org/W2004079116","https://openalex.org/W2035444316","https://openalex.org/W2078740228","https://openalex.org/W2080267935","https://openalex.org/W2100083403","https://openalex.org/W2102245417","https://openalex.org/W2105388068","https://openalex.org/W2107197127","https://openalex.org/W2108077002","https://openalex.org/W2114242761","https://openalex.org/W2120634758","https://openalex.org/W2123192957","https://openalex.org/W2129183345","https://openalex.org/W2141501391","https://openalex.org/W2149479807","https://openalex.org/W2151236218","https://openalex.org/W2153163936","https://openalex.org/W2156028445","https://openalex.org/W2160983885","https://openalex.org/W2163638465","https://openalex.org/W2165698417","https://openalex.org/W2170227286","https://openalex.org/W2427843410","https://openalex.org/W2520093650","https://openalex.org/W3150081868","https://openalex.org/W4237055875","https://openalex.org/W4250447890","https://openalex.org/W4253141837","https://openalex.org/W4255968055","https://openalex.org/W4378744510","https://openalex.org/W6651494351","https://openalex.org/W6676486999"],"related_works":["https://openalex.org/W2552408918","https://openalex.org/W2052585438","https://openalex.org/W2096785857","https://openalex.org/W1489971362","https://openalex.org/W257150968","https://openalex.org/W2096484761","https://openalex.org/W3140601928","https://openalex.org/W1977451125","https://openalex.org/W2168612648","https://openalex.org/W2168881618"],"abstract_inverted_index":null,"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}