{"id":"https://openalex.org/W1493614698","doi":"https://doi.org/10.1016/s0927-5452(05)80010-3","title":"The \u201cMIND\u201d scalable PIM architecture","display_name":"The \u201cMIND\u201d scalable PIM architecture","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W1493614698","doi":"https://doi.org/10.1016/s0927-5452(05)80010-3","mag":"1493614698"},"language":"en","primary_location":{"id":"doi:10.1016/s0927-5452(05)80010-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0927-5452(05)80010-3","pdf_url":null,"source":{"id":"https://openalex.org/S4210175178","display_name":"Advances in parallel computing","issn_l":"0927-5452","issn":["0927-5452","1879-808X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Advances in Parallel Computing","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089056206","display_name":"Thomas Sterling","orcid":"https://orcid.org/0009-0000-3554-9931"},"institutions":[{"id":"https://openalex.org/I122411786","display_name":"California Institute of Technology","ror":"https://ror.org/05dxps055","country_code":"US","type":"education","lineage":["https://openalex.org/I122411786"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Thomas Sterling","raw_affiliation_strings":["Center for Advanced Computing Research, California Institute of Technology 1200 E. California Blvd., MC158-79, Pasadena, CA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Advanced Computing Research, California Institute of Technology 1200 E. California Blvd., MC158-79, Pasadena, CA, USA","institution_ids":["https://openalex.org/I122411786"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063129935","display_name":"Maciej Brodowicz","orcid":"https://orcid.org/0000-0002-7154-8642"},"institutions":[{"id":"https://openalex.org/I122411786","display_name":"California Institute of Technology","ror":"https://ror.org/05dxps055","country_code":"US","type":"education","lineage":["https://openalex.org/I122411786"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Maciej Brodowicz","raw_affiliation_strings":["Center for Advanced Computing Research, California Institute of Technology 1200 E. California Blvd., MC158-79, Pasadena, CA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Advanced Computing Research, California Institute of Technology 1200 E. California Blvd., MC158-79, Pasadena, CA, USA","institution_ids":["https://openalex.org/I122411786"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5089056206"],"corresponding_institution_ids":["https://openalex.org/I122411786"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08819346,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"159","last_page":"183"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8094102144241333},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6448897123336792},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6076947450637817},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4687595069408417},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4238184988498688},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4158291518688202},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.41068679094314575},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3849782943725586},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.35866495966911316},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35423561930656433},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.3448057472705841},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.18435931205749512},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13815933465957642}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8094102144241333},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6448897123336792},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6076947450637817},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4687595069408417},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4238184988498688},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4158291518688202},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.41068679094314575},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3849782943725586},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.35866495966911316},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35423561930656433},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.3448057472705841},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18435931205749512},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13815933465957642},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0927-5452(05)80010-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0927-5452(05)80010-3","pdf_url":null,"source":{"id":"https://openalex.org/S4210175178","display_name":"Advances in parallel computing","issn_l":"0927-5452","issn":["0927-5452","1879-808X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Advances in Parallel Computing","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W70437322","https://openalex.org/W1588789843","https://openalex.org/W1896968490","https://openalex.org/W1983587324","https://openalex.org/W2056893810","https://openalex.org/W2081040934","https://openalex.org/W2094332102","https://openalex.org/W2098815550","https://openalex.org/W2112547256","https://openalex.org/W2112980698","https://openalex.org/W2117500680","https://openalex.org/W2119241866","https://openalex.org/W2130048397","https://openalex.org/W2130211963","https://openalex.org/W2141061712","https://openalex.org/W2143169490","https://openalex.org/W2145851359","https://openalex.org/W2155066383","https://openalex.org/W2156838587","https://openalex.org/W2158365276","https://openalex.org/W2538506363","https://openalex.org/W4231633798","https://openalex.org/W4285719527","https://openalex.org/W6635291042","https://openalex.org/W6670737489","https://openalex.org/W6674423026","https://openalex.org/W6677727411","https://openalex.org/W6680938981","https://openalex.org/W6681233612","https://openalex.org/W6728885212","https://openalex.org/W6811811721","https://openalex.org/W6903611192"],"related_works":["https://openalex.org/W254684032","https://openalex.org/W1848192231","https://openalex.org/W1974211070","https://openalex.org/W2934889147","https://openalex.org/W1942416056","https://openalex.org/W207100770","https://openalex.org/W4281924108","https://openalex.org/W1591576069","https://openalex.org/W4281569059","https://openalex.org/W1975698617"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}