{"id":"https://openalex.org/W2021673610","doi":"https://doi.org/10.1016/s0141-9331(98)00115-x","title":"An FPGA extension to ALU functions","display_name":"An FPGA extension to ALU functions","publication_year":1999,"publication_date":"1999-03-01","ids":{"openalex":"https://openalex.org/W2021673610","doi":"https://doi.org/10.1016/s0141-9331(98)00115-x","mag":"2021673610"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(98)00115-x","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(98)00115-x","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002307538","display_name":"Veselko Gu\u0161tin","orcid":null},"institutions":[{"id":"https://openalex.org/I153976015","display_name":"University of Ljubljana","ror":"https://ror.org/05njb9z20","country_code":"SI","type":"education","lineage":["https://openalex.org/I153976015"]}],"countries":["SI"],"is_corresponding":true,"raw_author_name":"Veselko Gustin","raw_affiliation_strings":["University of Ljubljana, Faculty of Computer and Information Science, Si-1000 Ljubljana, Trzaska 25, Slovenia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Ljubljana, Faculty of Computer and Information Science, Si-1000 Ljubljana, Trzaska 25, Slovenia","institution_ids":["https://openalex.org/I153976015"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5002307538"],"corresponding_institution_ids":["https://openalex.org/I153976015"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.14146495,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"22","issue":"9","first_page":"501","last_page":"508"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9757000207901001,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.954800009727478,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8677036762237549},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8420069217681885},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.6475337743759155},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.6424922943115234},{"id":"https://openalex.org/keywords/extension","display_name":"Extension (predicate logic)","score":0.603491485118866},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5423934459686279},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.408053994178772},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4024716913700104},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39166563749313354},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3656672537326813},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15906184911727905},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07792502641677856}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8677036762237549},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8420069217681885},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.6475337743759155},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.6424922943115234},{"id":"https://openalex.org/C2778029271","wikidata":"https://www.wikidata.org/wiki/Q5421931","display_name":"Extension (predicate logic)","level":2,"score":0.603491485118866},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5423934459686279},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.408053994178772},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4024716913700104},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39166563749313354},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3656672537326813},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15906184911727905},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07792502641677856}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0141-9331(98)00115-x","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(98)00115-x","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1545720541","https://openalex.org/W1597195064","https://openalex.org/W1678180485","https://openalex.org/W1991900639","https://openalex.org/W2003850193","https://openalex.org/W2042276850","https://openalex.org/W2074494064","https://openalex.org/W2092737755","https://openalex.org/W2109122299","https://openalex.org/W2165099691","https://openalex.org/W2611598995","https://openalex.org/W3112885076","https://openalex.org/W4253717004","https://openalex.org/W6608905145"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2367348190","https://openalex.org/W594316872","https://openalex.org/W2831860248","https://openalex.org/W2367794224","https://openalex.org/W2072850836","https://openalex.org/W2017163657","https://openalex.org/W1968650434","https://openalex.org/W2105610663","https://openalex.org/W1996607072"],"abstract_inverted_index":null,"counts_by_year":[{"year":2014,"cited_by_count":2}],"updated_date":"2026-08-08T01:25:22.217667","created_date":"2025-10-10T00:00:00"}