{"id":"https://openalex.org/W2048131019","doi":"https://doi.org/10.1016/s0141-9331(98)00048-9","title":"A scalable register file architecture for superscalar processors","display_name":"A scalable register file architecture for superscalar processors","publication_year":1998,"publication_date":"1998-06-01","ids":{"openalex":"https://openalex.org/W2048131019","doi":"https://doi.org/10.1016/s0141-9331(98)00048-9","mag":"2048131019"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(98)00048-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(98)00048-9","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042785962","display_name":"Steven Wallace","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},{"id":"https://openalex.org/I4210140791","display_name":"Irvine University","ror":"https://ror.org/04ysmca02","country_code":"US","type":"education","lineage":["https://openalex.org/I4210140791"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven Wallace","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Irvine, CA 92697, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Irvine, CA 92697, U.S.A","institution_ids":["https://openalex.org/I204250578","https://openalex.org/I4210140791"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012004974","display_name":"Nader Bagherzadeh","orcid":"https://orcid.org/0000-0001-7216-0546"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},{"id":"https://openalex.org/I4210140791","display_name":"Irvine University","ror":"https://ror.org/04ysmca02","country_code":"US","type":"education","lineage":["https://openalex.org/I4210140791"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nader Bagherzadeh","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, Irvine, CA 92697, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, Irvine, CA 92697, U.S.A","institution_ids":["https://openalex.org/I204250578","https://openalex.org/I4210140791"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1433549,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"22","issue":"1","first_page":"49","last_page":"60"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.9451322555541992},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9148656129837036},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.8470189571380615},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.6415574550628662},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5516555905342102},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5450419187545776},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5344293117523193},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.5195646286010742},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5080735683441162},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3732333183288574},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2066231667995453},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.0977182388305664},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.09602391719818115}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.9451322555541992},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9148656129837036},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.8470189571380615},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.6415574550628662},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5516555905342102},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5450419187545776},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5344293117523193},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.5195646286010742},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5080735683441162},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3732333183288574},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2066231667995453},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.0977182388305664},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.09602391719818115},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0141-9331(98)00048-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(98)00048-9","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1499323045","https://openalex.org/W1562342676","https://openalex.org/W1949410241","https://openalex.org/W1974374403","https://openalex.org/W2071568619","https://openalex.org/W2100350234","https://openalex.org/W2107916517","https://openalex.org/W2112324761","https://openalex.org/W2112833506","https://openalex.org/W2118532220","https://openalex.org/W2139172589","https://openalex.org/W2152622163","https://openalex.org/W2163935347","https://openalex.org/W3023634467","https://openalex.org/W3123681665","https://openalex.org/W6633566297","https://openalex.org/W6640745341","https://openalex.org/W6680545927","https://openalex.org/W6682317544","https://openalex.org/W6824151153"],"related_works":["https://openalex.org/W2224192221","https://openalex.org/W2356166161","https://openalex.org/W2483419948","https://openalex.org/W2048131019","https://openalex.org/W3088938565","https://openalex.org/W2117633822","https://openalex.org/W3149752743","https://openalex.org/W2097988171","https://openalex.org/W2914166553","https://openalex.org/W74994880"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
