{"id":"https://openalex.org/W1991358219","doi":"https://doi.org/10.1016/s0141-9331(98)00036-2","title":"Deadlock-free interval labelling","display_name":"Deadlock-free interval labelling","publication_year":1998,"publication_date":"1998-03-01","ids":{"openalex":"https://openalex.org/W1991358219","doi":"https://doi.org/10.1016/s0141-9331(98)00036-2","mag":"1991358219"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(98)00036-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(98)00036-2","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044731037","display_name":"M. Firth","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Mark A. Firth","raw_affiliation_strings":["PACT (Partnership in Advanced Computer Technologies), Park Row, Bristol BSI 5UB, UK"],"affiliations":[{"raw_affiliation_string":"PACT (Partnership in Advanced Computer Technologies), Park Row, Bristol BSI 5UB, UK","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103028874","display_name":"A. Jones","orcid":"https://orcid.org/0000-0002-5157-0762"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Andrew Jones","raw_affiliation_strings":["PACT (Partnership in Advanced Computer Technologies), Park Row, Bristol BSI 5UB, UK"],"affiliations":[{"raw_affiliation_string":"PACT (Partnership in Advanced Computer Technologies), Park Row, Bristol BSI 5UB, UK","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5044731037"],"corresponding_institution_ids":[],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":1.0575,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.75112663,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"21","issue":"7-8","first_page":"441","last_page":"454"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.898104190826416},{"id":"https://openalex.org/keywords/labelling","display_name":"Labelling","score":0.8804299831390381},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.7126001119613647},{"id":"https://openalex.org/keywords/interval","display_name":"Interval (graph theory)","score":0.6875250935554504},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6539850234985352},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.47528043389320374},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.46064358949661255},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4154803156852722},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2537907660007477},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.18089014291763306},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08441463112831116},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.05023506283760071}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.898104190826416},{"id":"https://openalex.org/C2780523633","wikidata":"https://www.wikidata.org/wiki/Q380709","display_name":"Labelling","level":2,"score":0.8804299831390381},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.7126001119613647},{"id":"https://openalex.org/C2778067643","wikidata":"https://www.wikidata.org/wiki/Q166507","display_name":"Interval (graph theory)","level":2,"score":0.6875250935554504},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6539850234985352},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.47528043389320374},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.46064358949661255},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4154803156852722},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2537907660007477},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.18089014291763306},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08441463112831116},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.05023506283760071},{"id":"https://openalex.org/C144024400","wikidata":"https://www.wikidata.org/wiki/Q21201","display_name":"Sociology","level":0,"score":0.0},{"id":"https://openalex.org/C73484699","wikidata":"https://www.wikidata.org/wiki/Q161733","display_name":"Criminology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0141-9331(98)00036-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(98)00036-2","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2340365916","https://openalex.org/W2914484629"],"related_works":["https://openalex.org/W1976633635","https://openalex.org/W2396436470","https://openalex.org/W4241622628","https://openalex.org/W1970064489","https://openalex.org/W2070829827","https://openalex.org/W2078502149","https://openalex.org/W2036642414","https://openalex.org/W1991894391","https://openalex.org/W2380886523","https://openalex.org/W2911482696"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}