{"id":"https://openalex.org/W2084957735","doi":"https://doi.org/10.1016/s0141-9331(97)01116-2","title":"Efficient automatic code generation for embedded systems","display_name":"Efficient automatic code generation for embedded systems","publication_year":1997,"publication_date":"1997-04-01","ids":{"openalex":"https://openalex.org/W2084957735","doi":"https://doi.org/10.1016/s0141-9331(97)01116-2","mag":"2084957735"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(97)01116-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(97)01116-2","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075779016","display_name":"D. Pilaud","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156361","display_name":"Verimag","ror":"https://ror.org/05afmzm11","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210156361","https://openalex.org/I4210159245","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"D. Pilaud","raw_affiliation_strings":["Verilog, Agence Rhone-Alpes, Centre Equation, 2 rue de Vignate-38610 Gieres, France"],"affiliations":[{"raw_affiliation_string":"Verilog, Agence Rhone-Alpes, Centre Equation, 2 rue de Vignate-38610 Gieres, France","institution_ids":["https://openalex.org/I4210156361"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5075779016"],"corresponding_institution_ids":["https://openalex.org/I4210156361"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.16570681,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"20","issue":"8","first_page":"501","last_page":"504"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9296610355377197},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.6925089359283447},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5776861310005188},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5750488042831421},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5544115304946899},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4122438430786133},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3253980875015259},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.19068032503128052},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.0778147280216217},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.06920841336250305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9296610355377197},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.6925089359283447},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5776861310005188},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5750488042831421},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5544115304946899},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4122438430786133},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3253980875015259},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.19068032503128052},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0778147280216217},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.06920841336250305},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0141-9331(97)01116-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(97)01116-2","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1999837403","https://openalex.org/W2045291808","https://openalex.org/W2125415493","https://openalex.org/W2159542925","https://openalex.org/W6661815652","https://openalex.org/W6683552124"],"related_works":["https://openalex.org/W1761969858","https://openalex.org/W2371211312","https://openalex.org/W2391470376","https://openalex.org/W2118330589","https://openalex.org/W2159551383","https://openalex.org/W2471362132","https://openalex.org/W2163672025","https://openalex.org/W2258184894","https://openalex.org/W2048831961","https://openalex.org/W1606349578"],"abstract_inverted_index":null,"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
