{"id":"https://openalex.org/W2018431509","doi":"https://doi.org/10.1016/s0141-9331(97)00051-3","title":"Low-power memory hierarchies: an argument for second-level caches","display_name":"Low-power memory hierarchies: an argument for second-level caches","publication_year":1998,"publication_date":"1998-02-01","ids":{"openalex":"https://openalex.org/W2018431509","doi":"https://doi.org/10.1016/s0141-9331(97)00051-3","mag":"2018431509"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(97)00051-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(97)00051-3","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111902481","display_name":"J. Kelly Flanagan","orcid":null},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"J.Kelly Flanagan","raw_affiliation_strings":["Computer Science Department, Brigham Young University, Provo, UT 84602, U.S.A","Computer Science Department Brigham Young University Provo, UT 84602, U.S.A.#TAB#"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, Brigham Young University, Provo, UT 84602, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Computer Science Department Brigham Young University Provo, UT 84602, U.S.A.#TAB#","institution_ids":["https://openalex.org/I100005738"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054138257","display_name":"James K. Archibald","orcid":"https://orcid.org/0000-0003-4190-8827"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"James K. Archibald","raw_affiliation_strings":["Electrical and Computer Engineering Department, Brigham Young University, Provo, UT 84602, U.S.A"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Brigham Young University, Provo, UT 84602, U.S.A","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100537226","display_name":"Jun Su","orcid":"https://orcid.org/0009-0001-8394-1839"},"institutions":[{"id":"https://openalex.org/I100005738","display_name":"Brigham Young University","ror":"https://ror.org/047rhhm47","country_code":"US","type":"education","lineage":["https://openalex.org/I100005738"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jun Su","raw_affiliation_strings":["Computer Science Department, Brigham Young University, Provo, UT 84602, U.S.A","Computer Science Department Brigham Young University Provo, UT 84602, U.S.A.#TAB#"],"affiliations":[{"raw_affiliation_string":"Computer Science Department, Brigham Young University, Provo, UT 84602, U.S.A","institution_ids":[]},{"raw_affiliation_string":"Computer Science Department Brigham Young University Provo, UT 84602, U.S.A.#TAB#","institution_ids":["https://openalex.org/I100005738"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111902481"],"corresponding_institution_ids":["https://openalex.org/I100005738"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.739,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.73160596,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"21","issue":"5","first_page":"279","last_page":"290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8897542953491211},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6206638216972351},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5284960865974426},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5279335379600525},{"id":"https://openalex.org/keywords/idle","display_name":"Idle","score":0.5272506475448608},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4680083990097046},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.4534171223640442},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44349780678749084},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4364728629589081},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4320238530635834},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.42651310563087463},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3748939335346222},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3534654974937439},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3085777163505554},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.2048514187335968}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8897542953491211},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6206638216972351},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5284960865974426},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5279335379600525},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.5272506475448608},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4680083990097046},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.4534171223640442},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44349780678749084},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4364728629589081},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4320238530635834},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.42651310563087463},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3748939335346222},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3534654974937439},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3085777163505554},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2048514187335968},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1016/s0141-9331(97)00051-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(97)00051-3","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.3.9611","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.3.9611","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://pel.cs.byu.edu/pubs/flanagan98/flanagan98.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.64.1916","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.64.1916","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://pel.cs.byu.edu/pubs/flanagan98/flanagan98.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7699999809265137}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W181569815","https://openalex.org/W1499849351","https://openalex.org/W1557863631","https://openalex.org/W1584049700","https://openalex.org/W1810183241","https://openalex.org/W1990397567","https://openalex.org/W2134385063","https://openalex.org/W2143632005","https://openalex.org/W2144189466","https://openalex.org/W2294693415","https://openalex.org/W3150149233","https://openalex.org/W6607372317","https://openalex.org/W6633294256","https://openalex.org/W6638193475","https://openalex.org/W6647847341","https://openalex.org/W6674524430","https://openalex.org/W6680132748","https://openalex.org/W6681318113","https://openalex.org/W6681337699"],"related_works":["https://openalex.org/W4238754064","https://openalex.org/W2155373950","https://openalex.org/W2354036839","https://openalex.org/W4243618206","https://openalex.org/W2044064773","https://openalex.org/W2138825797","https://openalex.org/W4242495027","https://openalex.org/W3093911585","https://openalex.org/W2564569739","https://openalex.org/W1975444747"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
