{"id":"https://openalex.org/W1969504147","doi":"https://doi.org/10.1016/s0141-9331(97)00003-3","title":"BOAR: an advanced HW/SW coemulation environment for DSP system development","display_name":"BOAR: an advanced HW/SW coemulation environment for DSP system development","publication_year":1997,"publication_date":"1997-07-01","ids":{"openalex":"https://openalex.org/W1969504147","doi":"https://doi.org/10.1016/s0141-9331(97)00003-3","mag":"1969504147"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(97)00003-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(97)00003-3","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055846108","display_name":"Jouni Isoaho","orcid":"https://orcid.org/0000-0002-5789-3992"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Jouni Isoaho","raw_affiliation_strings":["Royal Institute of Technology, Electronic System Design ESDLab/KTH-ELECTRUM, Electrum 229, S-164 40 Kista, Sweden"],"affiliations":[{"raw_affiliation_string":"Royal Institute of Technology, Electronic System Design ESDLab/KTH-ELECTRUM, Electrum 229, S-164 40 Kista, Sweden","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007360768","display_name":"Vesa K\u00f6pp\u00e4","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Vesa K\u00f6pp\u00e4","raw_affiliation_strings":["Tampere University of Technology, Signal Processing Laboratory P.O.Box 553, FIN-33101 Tampere, Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Signal Processing Laboratory P.O.Box 553, FIN-33101 Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052356741","display_name":"Jarkko Oksala","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Jarkko Oksala","raw_affiliation_strings":["Tampere University of Technology, Signal Processing Laboratory P.O.Box 553, FIN-33101 Tampere, Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Signal Processing Laboratory P.O.Box 553, FIN-33101 Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109927934","display_name":"Pasi Ojala","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133110","display_name":"Tampere University","ror":null,"country_code":"FI","type":null,"lineage":["https://openalex.org/I4210133110"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Pasi Ojala","raw_affiliation_strings":["Tampere University of Technology, Signal Processing Laboratory P.O.Box 553, FIN-33101 Tampere, Finland"],"affiliations":[{"raw_affiliation_string":"Tampere University of Technology, Signal Processing Laboratory P.O.Box 553, FIN-33101 Tampere, Finland","institution_ids":["https://openalex.org/I4210133110"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5055846108"],"corresponding_institution_ids":["https://openalex.org/I86987016"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.09659686,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"20","issue":"10","first_page":"607","last_page":"615"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8945512175559998},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6679971814155579},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4761464595794678},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3300333023071289}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8945512175559998},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6679971814155579},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4761464595794678},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3300333023071289}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/s0141-9331(97)00003-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/s0141-9331(97)00003-3","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W4470474","https://openalex.org/W1465211442","https://openalex.org/W1466979986","https://openalex.org/W1608108321","https://openalex.org/W1735031787","https://openalex.org/W1861573487","https://openalex.org/W2007173547","https://openalex.org/W2054918342","https://openalex.org/W2073075989","https://openalex.org/W2135100153","https://openalex.org/W2143007938","https://openalex.org/W2161455936","https://openalex.org/W2163549407","https://openalex.org/W2475540910","https://openalex.org/W2611556824","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2147481850","https://openalex.org/W2387078853","https://openalex.org/W2374455716","https://openalex.org/W2363990172"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
