{"id":"https://openalex.org/W2126951324","doi":"https://doi.org/10.1016/s0141-9331(03)00095-4","title":"Adding synchronous and LSSD modes to asynchronous circuits","display_name":"Adding synchronous and LSSD modes to asynchronous circuits","publication_year":2003,"publication_date":"2003-06-09","ids":{"openalex":"https://openalex.org/W2126951324","doi":"https://doi.org/10.1016/s0141-9331(03)00095-4","mag":"2126951324"},"language":"en","primary_location":{"id":"doi:10.1016/s0141-9331(03)00095-4","is_oa":true,"landing_page_url":"https://doi.org/10.1016/s0141-9331(03)00095-4","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0141933103000954","source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://www.sciencedirect.com/science/article/pii/S0141933103000954","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030371220","display_name":"Kees van Berkel","orcid":"https://orcid.org/0000-0002-5246-1824"},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Kees van Berkel","raw_affiliation_strings":["Eindhoven University of Technology, Eindhoven, The Netherlands","Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Eindhoven University of Technology, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086576969","display_name":"A. Peeters","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Ad Peeters","raw_affiliation_strings":["Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands","Philips Research Laboratories , Prof. Holstlaan 4 , 5656 AA Eindhoven , The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I4210122849"]},{"raw_affiliation_string":"Philips Research Laboratories , Prof. Holstlaan 4 , 5656 AA Eindhoven , The Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086193965","display_name":"Frank te Beest","orcid":null},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Frank te Beest","raw_affiliation_strings":["University of Twente, Enschede, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Twente, Enschede, The Netherlands","institution_ids":["https://openalex.org/I94624287"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030371220"],"corresponding_institution_ids":["https://openalex.org/I4210122849","https://openalex.org/I83019370"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":1.4499,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.8415628,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"27","issue":"9","first_page":"461","last_page":"471"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8506786823272705},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8218567967414856},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7955848574638367},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6509904861450195},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5729761719703674},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5508975982666016},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5289756655693054},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4943678379058838},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.48982736468315125},{"id":"https://openalex.org/keywords/synchronizer","display_name":"Synchronizer","score":0.45938876271247864},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.42507797479629517},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39218950271606445},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2383655607700348},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.23413482308387756},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19240400195121765},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17501300573349},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15046429634094238},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.07472562789916992},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.07302144169807434},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.06270456314086914}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8506786823272705},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8218567967414856},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7955848574638367},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6509904861450195},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5729761719703674},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5508975982666016},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5289756655693054},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4943678379058838},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.48982736468315125},{"id":"https://openalex.org/C66727535","wikidata":"https://www.wikidata.org/wiki/Q7662199","display_name":"Synchronizer","level":2,"score":0.45938876271247864},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.42507797479629517},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39218950271606445},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2383655607700348},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.23413482308387756},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19240400195121765},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17501300573349},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15046429634094238},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.07472562789916992},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.07302144169807434},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.06270456314086914},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1016/s0141-9331(03)00095-4","is_oa":true,"landing_page_url":"https://doi.org/10.1016/s0141-9331(03)00095-4","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0141933103000954","source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/f8d43208-1419-4917-b33b-4c19ec5ad553","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/f8d43208-1419-4917-b33b-4c19ec5ad553","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Berkel, van, C H, Peeters, A M G & Beest, te, F 2003, 'Adding synchronous and LSSD modes to asynchronous circuits', Microprocessors and Microsystems, vol. 27, no. 9, pp. 461-471. https://doi.org/10.1016/S0141-9331(03)00095-4","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:ris.utwente.nl:openaire_cris_publications/f2ff2870-9396-4692-a406-50bc29860c61","is_oa":false,"landing_page_url":"https://research.utwente.nl/en/publications/f2ff2870-9396-4692-a406-50bc29860c61","pdf_url":null,"source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"van Berkel, K, Peeters, A & te Beest, F J 2003, 'Adding synchronous and LSSD modes to asynchronous circuits', Microprocessors and microsystems, vol. 27, no. 9, pp. 461-471. https://doi.org/10.1016/S0141-9331(03)00095-4","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:tue:oai:pure.tue.nl:publications/f8d43208-1419-4917-b33b-4c19ec5ad553","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/f8d43208-1419-4917-b33b-4c19ec5ad553","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Microprocessors and Microsystems, 27(9), 461 - 471. Elsevier","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.1016/s0141-9331(03)00095-4","is_oa":true,"landing_page_url":"https://doi.org/10.1016/s0141-9331(03)00095-4","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0141933103000954","source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320321800","display_name":"Nederlandse Organisatie voor Wetenschappelijk Onderzoek","ror":"https://ror.org/04jsz6e67"},{"id":"https://openalex.org/F4320334893","display_name":"Stichting voor de Technische Wetenschappen","ror":"https://ror.org/057tq3593"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2126951324.pdf","grobid_xml":"https://content.openalex.org/works/W2126951324.grobid-xml"},"referenced_works_count":22,"referenced_works":["https://openalex.org/W70061769","https://openalex.org/W1486202357","https://openalex.org/W1533710763","https://openalex.org/W1679970298","https://openalex.org/W1765538419","https://openalex.org/W2002058428","https://openalex.org/W2006097283","https://openalex.org/W2035720669","https://openalex.org/W2066974842","https://openalex.org/W2073076521","https://openalex.org/W2100382727","https://openalex.org/W2110259743","https://openalex.org/W2161849579","https://openalex.org/W2166402441","https://openalex.org/W2597881196","https://openalex.org/W3210523556","https://openalex.org/W4242530255","https://openalex.org/W4285719527","https://openalex.org/W6602845172","https://openalex.org/W6637799165","https://openalex.org/W6667023711","https://openalex.org/W6802779965"],"related_works":["https://openalex.org/W2095703739","https://openalex.org/W364924225","https://openalex.org/W1993985975","https://openalex.org/W2093992207","https://openalex.org/W2325117947","https://openalex.org/W2384756109","https://openalex.org/W628161287","https://openalex.org/W158833317","https://openalex.org/W794031490","https://openalex.org/W2349909378"],"abstract_inverted_index":null,"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}