{"id":"https://openalex.org/W7155542672","doi":"https://doi.org/10.1016/j.vlsi.2026.102749","title":"A novel RISC-V core for the networking processing processor with bit-level custom instructions and thread-aware fetching architecture","display_name":"A novel RISC-V core for the networking processing processor with bit-level custom instructions and thread-aware fetching architecture","publication_year":2026,"publication_date":"2026-04-24","ids":{"openalex":"https://openalex.org/W7155542672","doi":"https://doi.org/10.1016/j.vlsi.2026.102749"},"language":"en","primary_location":{"id":"doi:10.1016/j.vlsi.2026.102749","is_oa":false,"landing_page_url":"https://doi.org/10.1016/j.vlsi.2026.102749","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5134474133","display_name":"Jiakun Chen","orcid":"https://orcid.org/0009-0003-4128-3115"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiakun Chen","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing 211189, China"],"raw_orcid":"https://orcid.org/0009-0003-4128-3115","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing 211189, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5134507022","display_name":"Yuanming Fu","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuanming Fu","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing 211189, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing 211189, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109299523","display_name":"Yi Lian","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuyu Lian","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing 211189, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing 211189, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5134550020","display_name":"Jianhui Han","orcid":null},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianhui Han","raw_affiliation_strings":["Sanechips Technology Co., Ltd., Shenzhen 518057, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sanechips Technology Co., Ltd., Shenzhen 518057, China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067016449","display_name":"Jianyuan Pi","orcid":"https://orcid.org/0000-0002-5419-9145"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianyuan Pi","raw_affiliation_strings":["Sanechips Technology Co., Ltd., Shenzhen 518057, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sanechips Technology Co., Ltd., Shenzhen 518057, China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5134468091","display_name":"Ming Ling","orcid":null},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Ming Ling","raw_affiliation_strings":["School of Integrated Circuits, Southeast University, Nanjing 211189, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Southeast University, Nanjing 211189, China","institution_ids":["https://openalex.org/I76569877"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5134468091"],"corresponding_institution_ids":["https://openalex.org/I76569877"],"apc_list":{"value":2150,"currency":"USD","value_usd":2150},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.90869763,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"109","issue":null,"first_page":"102749","last_page":"102749"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.7732999920845032,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.7732999920845032,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.08179999887943268,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.038100000470876694,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5519000291824341},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5031999945640564},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.46630001068115234},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.41119998693466187},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.3571000099182129},{"id":"https://openalex.org/keywords/systems-architecture","display_name":"Systems architecture","score":0.3131999969482422},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.3012000024318695}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6866999864578247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5810999870300293},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5519000291824341},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5031999945640564},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5024999976158142},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.46630001068115234},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.41119998693466187},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.3571000099182129},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34709998965263367},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31869998574256897},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.3131999969482422},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.3012000024318695},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.29280000925064087},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2856999933719635},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.28529998660087585},{"id":"https://openalex.org/C52027705","wikidata":"https://www.wikidata.org/wiki/Q6805986","display_name":"Media processor","level":4,"score":0.2754000127315521},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2632000148296356},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.25619998574256897}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/j.vlsi.2026.102749","is_oa":false,"landing_page_url":"https://doi.org/10.1016/j.vlsi.2026.102749","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6004740595817566,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2090584832","https://openalex.org/W2168681242","https://openalex.org/W3042964438","https://openalex.org/W4293182269","https://openalex.org/W4321381226","https://openalex.org/W4395027885"],"related_works":[],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-05-04T06:00:05.808912","created_date":"2026-04-25T00:00:00"}
