{"id":"https://openalex.org/W2338293335","doi":"https://doi.org/10.1016/j.cpc.2016.04.006","title":"Modern multicore and manycore architectures: Modelling, optimisation and benchmarking a multiblock CFD code","display_name":"Modern multicore and manycore architectures: Modelling, optimisation and benchmarking a multiblock CFD code","publication_year":2016,"publication_date":"2016-04-29","ids":{"openalex":"https://openalex.org/W2338293335","doi":"https://doi.org/10.1016/j.cpc.2016.04.006","mag":"2338293335"},"language":"en","primary_location":{"id":"doi:10.1016/j.cpc.2016.04.006","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.cpc.2016.04.006","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0010465516300959/pdf","source":{"id":"https://openalex.org/S142305363","display_name":"Computer Physics Communications","issn_l":"0010-4655","issn":["0010-4655","1879-2944"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer Physics Communications","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://www.sciencedirect.com/science/article/pii/S0010465516300959/pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053716079","display_name":"Ioan Hadade","orcid":"https://orcid.org/0000-0002-9049-1952"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]},{"id":"https://openalex.org/I866009140","display_name":"Rolls-Royce (United Kingdom)","ror":"https://ror.org/04h08p482","country_code":"GB","type":"company","lineage":["https://openalex.org/I866009140"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Ioan Hadade","raw_affiliation_strings":["Whole Engine Modelling Group, Rolls\u2013Royce Vibration UTC, Mechanical Engineering Department, Imperial College London, South Kensington, SW7 2AZ, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Whole Engine Modelling Group, Rolls\u2013Royce Vibration UTC, Mechanical Engineering Department, Imperial College London, South Kensington, SW7 2AZ, London, United Kingdom","institution_ids":["https://openalex.org/I47508984","https://openalex.org/I866009140"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109177070","display_name":"Luca di Mare","orcid":null},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]},{"id":"https://openalex.org/I866009140","display_name":"Rolls-Royce (United Kingdom)","ror":"https://ror.org/04h08p482","country_code":"GB","type":"company","lineage":["https://openalex.org/I866009140"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Luca di Mare","raw_affiliation_strings":["Whole Engine Modelling Group , Rolls-Royce Vibration UTC , Mechanical Engineering Department , Imperial College London , South Kensington , SW7 2AZ , London , United Kingdom","Whole Engine Modelling Group, Rolls\u2013Royce Vibration UTC, Mechanical Engineering Department, Imperial College London, South Kensington, SW7 2AZ, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Whole Engine Modelling Group , Rolls-Royce Vibration UTC , Mechanical Engineering Department , Imperial College London , South Kensington , SW7 2AZ , London , United Kingdom","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Whole Engine Modelling Group, Rolls\u2013Royce Vibration UTC, Mechanical Engineering Department, Imperial College London, South Kensington, SW7 2AZ, London, United Kingdom","institution_ids":["https://openalex.org/I47508984","https://openalex.org/I866009140"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5053716079"],"corresponding_institution_ids":["https://openalex.org/I47508984","https://openalex.org/I866009140"],"apc_list":{"value":3670,"currency":"USD","value_usd":3670},"apc_paid":{"value":2411,"currency":"EUR","value_usd":2600},"fwci":3.884,"has_fulltext":true,"cited_by_count":13,"citation_normalized_percentile":{"value":0.92599687,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"205","issue":null,"first_page":"32","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9807000160217285,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.9040288925170898},{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.884395956993103},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8202566504478455},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.7527101635932922},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7089331150054932},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6393136978149414},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5917688608169556},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5856932401657104},{"id":"https://openalex.org/keywords/data-parallelism","display_name":"Data parallelism","score":0.5090115070343018},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.49137845635414124},{"id":"https://openalex.org/keywords/task-parallelism","display_name":"Task parallelism","score":0.465703547000885},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.46071088314056396},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.44611671566963196},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.424702525138855},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4169139564037323},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.2730075418949127},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11826881766319275}],"concepts":[{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.9040288925170898},{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.884395956993103},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8202566504478455},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.7527101635932922},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7089331150054932},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6393136978149414},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5917688608169556},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5856932401657104},{"id":"https://openalex.org/C61483411","wikidata":"https://www.wikidata.org/wiki/Q3124522","display_name":"Data parallelism","level":3,"score":0.5090115070343018},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.49137845635414124},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.465703547000885},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.46071088314056396},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.44611671566963196},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.424702525138855},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4169139564037323},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.2730075418949127},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11826881766319275},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1016/j.cpc.2016.04.006","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.cpc.2016.04.006","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0010465516300959/pdf","source":{"id":"https://openalex.org/S142305363","display_name":"Computer Physics Communications","issn_l":"0010-4655","issn":["0010-4655","1879-2944"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer Physics Communications","raw_type":"journal-article"},{"id":"pmh:oai:ora.ox.ac.uk:uuid:0e64334f-85a8-4ba4-a89d-aa7e02b889d4","is_oa":true,"landing_page_url":"https://ora.ox.ac.uk/objects/uuid:0e64334f-85a8-4ba4-a89d-aa7e02b889d4","pdf_url":null,"source":{"id":"https://openalex.org/S4306402636","display_name":"Oxford University Research Archive (ORA) (University of Oxford)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I40120149","host_organization_name":"University of Oxford","host_organization_lineage":["https://openalex.org/I40120149"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Journal article"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/30932","is_oa":true,"landing_page_url":"http://hdl.handle.net/10044/1/30932","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"47","raw_type":"Journal Article"}],"best_oa_location":{"id":"doi:10.1016/j.cpc.2016.04.006","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.cpc.2016.04.006","pdf_url":"https://www.sciencedirect.com/science/article/pii/S0010465516300959/pdf","source":{"id":"https://openalex.org/S142305363","display_name":"Computer Physics Communications","issn_l":"0010-4655","issn":["0010-4655","1879-2944"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer Physics Communications","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5663254522","display_name":null,"funder_award_id":"13220161","funder_id":"https://openalex.org/F4320320288","funder_display_name":"Rolls-Royce"},{"id":"https://openalex.org/G876650398","display_name":null,"funder_award_id":"13220161","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320320283","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10"},{"id":"https://openalex.org/F4320320288","display_name":"Rolls-Royce","ror":"https://ror.org/04h08p482"},{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2338293335.pdf","grobid_xml":"https://content.openalex.org/works/W2338293335.grobid-xml"},"referenced_works_count":29,"referenced_works":["https://openalex.org/W282151396","https://openalex.org/W348433680","https://openalex.org/W654576583","https://openalex.org/W1487934326","https://openalex.org/W1493774699","https://openalex.org/W1507795625","https://openalex.org/W1567646530","https://openalex.org/W1895381303","https://openalex.org/W2002555321","https://openalex.org/W2008373862","https://openalex.org/W2038983366","https://openalex.org/W2039417226","https://openalex.org/W2043057066","https://openalex.org/W2049009664","https://openalex.org/W2054961017","https://openalex.org/W2063517087","https://openalex.org/W2079342791","https://openalex.org/W2079498535","https://openalex.org/W2491027815","https://openalex.org/W2498043873","https://openalex.org/W2501390808","https://openalex.org/W2911830835","https://openalex.org/W2911831466","https://openalex.org/W2942999856","https://openalex.org/W3023718405","https://openalex.org/W4205474951","https://openalex.org/W4245037559","https://openalex.org/W4248073216","https://openalex.org/W4250876596"],"related_works":["https://openalex.org/W4240606930","https://openalex.org/W2526302199","https://openalex.org/W2003935582","https://openalex.org/W3007272028","https://openalex.org/W2950520577","https://openalex.org/W2040503315","https://openalex.org/W1229628","https://openalex.org/W2468095077","https://openalex.org/W168408236","https://openalex.org/W2494130044"],"abstract_inverted_index":{"Modern":[0],"multicore":[1,62,191,215],"and":[2,43,60,64,90,122,128,193,204,217],"manycore":[3,225],"processors":[4,216],"exhibit":[5],"multiple":[6],"levels":[7],"of":[8,14,31,52,87,93,142,210],"parallelism":[9,33,133],"through":[10,136],"a":[11,53,140,208],"wide":[12],"range":[13],"architectural":[15],"features":[16],"such":[17],"as":[18],"SIMD":[19,110,120],"for":[20,26,37,107,112,124,173,181],"data":[21],"parallel":[22],"execution":[23,184],"or":[24],"threads":[25],"core":[27],"parallelism.":[28],"The":[29],"exploitation":[30],"multi-level":[32],"is":[34,134],"therefore":[35],"crucial":[36],"achieving":[38,108],"superior":[39],"performance":[40,50,165],"on":[41,57,77,139,189,195,213,221],"current":[42],"future":[44],"processors.":[45],"This":[46],"paper":[47],"presents":[48],"the":[49,65,85,91,94,103,116,163,190,196,214,222],"tuning":[51],"multiblock":[54],"CFD":[55],"solver":[56],"Intel":[58,66],"SandyBridge":[59],"Haswell":[61],"CPUs":[63,192],"Xeon":[67,197,223],"Phi":[68,198,224],"Knights":[69],"Corner":[70],"coprocessor.":[71,199,226],"Code":[72],"optimisations":[73,148],"have":[74],"been":[75],"applied":[76],"two":[78],"computational":[79,83],"kernels":[80,114],"exhibiting":[81],"different":[82],"patterns:":[84],"update":[86],"flow":[88],"variables":[89],"evaluation":[92],"Roe":[95],"numerical":[96],"fluxes.":[97],"We":[98,177],"discuss":[99],"at":[100,201],"great":[101],"length":[102],"code":[104],"transformations":[105],"required":[106],"efficient":[109],"computations":[111,127],"both":[113,186],"across":[115,185],"selected":[117],"devices":[118],"including":[119],"shuffles":[121],"transpositions":[123],"flux":[125],"stencil":[126],"global":[129],"memory":[130],"transformations.":[131],"Core":[132],"expressed":[135],"threading":[137],"based":[138],"number":[141],"domain":[143],"decomposition":[144],"techniques":[145],"together":[146],"with":[147,162],"pertaining":[149],"to":[150,169,219],"alleviating":[151],"NUMA":[152],"effects":[153],"found":[154],"in":[155,167],"multi-socket":[156],"compute":[157],"nodes.":[158],"Results":[159],"are":[160],"correlated":[161],"Roofline":[164],"model":[166],"order":[168],"assert":[170],"their":[171],"efficiency":[172],"each":[174],"distinct":[175],"architecture.":[176],"report":[178],"significant":[179],"speedups":[180],"single":[182],"thread":[183],"kernels:":[187],"2-5X":[188],"14-23X":[194],"Computations":[200],"full":[202],"node":[203],"chip":[205],"concurrency":[206],"deliver":[207],"factor":[209],"three":[211],"speedup":[212],"up":[218],"24X":[220]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":3}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}
