{"id":"https://openalex.org/W7147390609","doi":"https://doi.org/10.1016/j.compeleceng.2026.111152","title":"Physical design of a 32-bit RISC-V based microprocessor: A proof of concept for chaotic systems implementation","display_name":"Physical design of a 32-bit RISC-V based microprocessor: A proof of concept for chaotic systems implementation","publication_year":2026,"publication_date":"2026-04-01","ids":{"openalex":"https://openalex.org/W7147390609","doi":"https://doi.org/10.1016/j.compeleceng.2026.111152"},"language":"en","primary_location":{"id":"doi:10.1016/j.compeleceng.2026.111152","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.compeleceng.2026.111152","pdf_url":null,"source":{"id":"https://openalex.org/S121340289","display_name":"Computers & Electrical Engineering","issn_l":"0045-7906","issn":["0045-7906","1879-0755"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computers and Electrical Engineering","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1016/j.compeleceng.2026.111152","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5132566089","display_name":"Noe Reyes-Ortiz","orcid":null},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Noe Reyes-Ortiz","raw_affiliation_strings":["Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132605982","display_name":"Daniel Clemente-Lopez","orcid":null},"institutions":[{"id":"https://openalex.org/I189843002","display_name":"Instituto Tecnol\u00f3gico de Saltillo","ror":"https://ror.org/04vbyvm90","country_code":"MX","type":"education","lineage":["https://openalex.org/I189843002"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Daniel Clemente-Lopez","raw_affiliation_strings":["SECIHTI-InnovaBienestar de Mexico, Saltillo, 25290, Mexico"],"raw_orcid":"https://orcid.org/0000-0002-1377-510X","affiliations":[{"raw_affiliation_string":"SECIHTI-InnovaBienestar de Mexico, Saltillo, 25290, Mexico","institution_ids":["https://openalex.org/I189843002"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5128410806","display_name":"Jos\u00e9 de Jesus Rangel-Magdaleno","orcid":null},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":true,"raw_author_name":"Jose de Jesus Rangel-Magdaleno","raw_affiliation_strings":["Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico"],"raw_orcid":"https://orcid.org/0000-0003-2785-5060","affiliations":[{"raw_affiliation_string":"Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034708346","display_name":"Sergio A. Rosales-Nunez","orcid":"https://orcid.org/0000-0002-5122-6371"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Sergio Rosales-Nunez","raw_affiliation_strings":["Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico"],"raw_orcid":"https://orcid.org/0000-0002-5122-6371","affiliations":[{"raw_affiliation_string":"Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5128579648","display_name":"J. H. Barron-Zambrano","orcid":null},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Jose Hugo Barron-Zambrano","raw_affiliation_strings":["Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Nacional de Astrof\u00edsica \u00d3ptica y Electr\u00f3nica, Digital Systems Group, Electronics Department, 72840 Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5128410806"],"corresponding_institution_ids":["https://openalex.org/I39824353"],"apc_list":{"value":3100,"currency":"USD","value_usd":3100},"apc_paid":{"value":3100,"currency":"USD","value_usd":3100},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.74145191,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"134","issue":null,"first_page":"111152","last_page":"111152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.31700000166893005,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.31700000166893005,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10244","display_name":"Chaos control and synchronization","score":0.18629999458789825,"subfield":{"id":"https://openalex.org/subfields/3109","display_name":"Statistical and Nonlinear Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.16599999368190765,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7264999747276306},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6574000120162964},{"id":"https://openalex.org/keywords/interrupt","display_name":"Interrupt","score":0.6100000143051147},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5900999903678894},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5726000070571899},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5435000061988831},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5202999711036682},{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.5128999948501587},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5044999718666077},{"id":"https://openalex.org/keywords/event","display_name":"Event (particle physics)","score":0.49000000953674316}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7264999747276306},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7006999850273132},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6574000120162964},{"id":"https://openalex.org/C41661131","wikidata":"https://www.wikidata.org/wiki/Q220764","display_name":"Interrupt","level":3,"score":0.6100000143051147},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5900999903678894},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5726000070571899},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5565999746322632},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5435000061988831},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5202999711036682},{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.5128999948501587},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5044999718666077},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.49000000953674316},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.4657000005245209},{"id":"https://openalex.org/C2777052490","wikidata":"https://www.wikidata.org/wiki/Q5072826","display_name":"Chaotic","level":2,"score":0.4471000134944916},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42419999837875366},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4074999988079071},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4018999934196472},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.36079999804496765},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.34700000286102295},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.3391999900341034},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.329800009727478},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3249000012874603},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.31029999256134033},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.2856000065803528},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.28529998660087585},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.27889999747276306},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2768000066280365},{"id":"https://openalex.org/C504728807","wikidata":"https://www.wikidata.org/wiki/Q180256","display_name":"Booting","level":2,"score":0.27410000562667847},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.2727000117301941},{"id":"https://openalex.org/C197115733","wikidata":"https://www.wikidata.org/wiki/Q1003136","display_name":"Forcing (mathematics)","level":2,"score":0.27000001072883606},{"id":"https://openalex.org/C116672817","wikidata":"https://www.wikidata.org/wiki/Q1454986","display_name":"Physical system","level":2,"score":0.2669999897480011},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.26429998874664307},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.258899986743927},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.25209999084472656},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.25040000677108765}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/j.compeleceng.2026.111152","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.compeleceng.2026.111152","pdf_url":null,"source":{"id":"https://openalex.org/S121340289","display_name":"Computers & Electrical Engineering","issn_l":"0045-7906","issn":["0045-7906","1879-0755"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computers and Electrical Engineering","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1016/j.compeleceng.2026.111152","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.compeleceng.2026.111152","pdf_url":null,"source":{"id":"https://openalex.org/S121340289","display_name":"Computers & Electrical Engineering","issn_l":"0045-7906","issn":["0045-7906","1879-0755"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computers and Electrical Engineering","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1551822527","https://openalex.org/W2000280087","https://openalex.org/W2162831449","https://openalex.org/W2936567838","https://openalex.org/W2941442404","https://openalex.org/W3188130968","https://openalex.org/W4247459146","https://openalex.org/W4285220288","https://openalex.org/W4306744182","https://openalex.org/W4407304417","https://openalex.org/W4408155613","https://openalex.org/W4409168256","https://openalex.org/W4409329963","https://openalex.org/W4410577555","https://openalex.org/W4412992741"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"the":[3,32,118,177],"physical":[4,128],"design":[5,73,129,173,197],"of":[6,31,152],"a":[7,15,29,39,50,76,105,123,149,182],"32-bit":[8,33,163],"RISC-V-based":[9],"microprocessor":[10,165],"(":[11],"\u03bc":[12,24,89],"P)":[13],"as":[14,122],"proof-of-concept":[16],"platform":[17],"for":[18],"implementing":[19],"chaotic":[20,120,191],"systems.":[21],"The":[22,72,88,126,172],"proposed":[23],"P":[25,90],"is":[26,169,174,199],"derived":[27],"from":[28,131,201],"subset":[30],"RISC-V":[34,164],"integer":[35],"ISA":[36,179],"and":[37,45,55,67,84,95,114,145,155,180],"adopts":[38],"Harvard":[40,183],"architecture":[41],"with":[42,166],"separate":[43],"instruction":[44,57,112],"data":[46],"memories.":[47],"It":[48],"incorporates":[49],"UART-DMA":[51],"bootloader":[52],"that":[53],"receives":[54],"stores":[56],"sequences":[58],"in":[59,93,148],"memory":[60,70],"without":[61],"processor":[62],"intervention,":[63],"accelerating":[64],"program":[65],"loading":[66],"reducing":[68],"internal":[69],"usage.":[71],"also":[74],"features":[75],"custom":[77],"interrupt":[78],"workflow":[79],"enabling":[80],"prioritized":[81],"event":[82],"handling":[83],"flexible":[85],"peripheral":[86,115],"integration.":[87],"was":[91,138],"described":[92],"Verilog-HDL":[94],"validated":[96],"using":[97,117,140],"Universal":[98],"Verification":[99],"Methodology":[100],"(UVM);":[101],"FPGA":[102],"prototyping":[103],"on":[104,176],"Nexys-4":[106],"DDR":[107],"board":[108],"further":[109],"corroborated":[110],"correct":[111],"execution":[113],"interaction":[116],"Lorenz":[119],"system":[121],"representative":[124],"workload.":[125],"complete":[127,195],"flow":[130,198],"RTL":[132,202],"synthesis":[133,203],"to":[134,204],"GDSII":[135,205],"layout":[136,150,156],"generation":[137],"performed":[139],"Cadence":[141],"tools":[142],"(Genus,":[143],"Innovus,":[144],"Virtuoso),":[146],"resulting":[147],"free":[151],"design-rule-check":[153],"(DRC)":[154],"versus":[157],"schematic":[158],"(LVS)":[159],"violations.":[160],"\u2022":[161,171,185,193],"A":[162,194],"integrated":[167],"peripherals":[168],"implemented.":[170],"based":[175],"RVI32":[178],"integrates":[181],"architecture.":[184],"Experimental":[186],"hardware":[187],"results":[188],"demonstrate":[189],"stable":[190],"behavior.":[192],"ASIC":[196],"demonstrated":[200],"generation.":[206]},"counts_by_year":[],"updated_date":"2026-04-02T13:53:19.096889","created_date":"2026-04-02T00:00:00"}
