{"id":"https://openalex.org/W1965034761","doi":"https://doi.org/10.1016/0743-7315(85)90019-x","title":"A VLSI structure for the deadlock avoidance problem","display_name":"A VLSI structure for the deadlock avoidance problem","publication_year":1985,"publication_date":"1985-11-01","ids":{"openalex":"https://openalex.org/W1965034761","doi":"https://doi.org/10.1016/0743-7315(85)90019-x","mag":"1965034761"},"language":"en","primary_location":{"id":"doi:10.1016/0743-7315(85)90019-x","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0743-7315(85)90019-x","pdf_url":null,"source":{"id":"https://openalex.org/S157146593","display_name":"Journal of Parallel and Distributed Computing","issn_l":"0743-7315","issn":["0743-7315","1096-0848"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Parallel and Distributed Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074793077","display_name":"Paola Bertolazzi","orcid":"https://orcid.org/0000-0002-2249-1993"},"institutions":[{"id":"https://openalex.org/I4210162062","display_name":"Istituto di Analisi dei Sistemi ed Informatica Antonio Ruberti","ror":"https://ror.org/054ye0e45","country_code":"IT","type":"facility","lineage":["https://openalex.org/I4210155236","https://openalex.org/I4210162062"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"P. Bertolazzi","raw_affiliation_strings":["Istituto di Analisi dei Sistemi ed Informatica del CNR, Viale Manzoni 30, 00185 Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Istituto di Analisi dei Sistemi ed Informatica del CNR, Viale Manzoni 30, 00185 Rome, Italy","institution_ids":["https://openalex.org/I4210162062"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113922466","display_name":"G. Bongiovanni","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G. Bongiovanni","raw_affiliation_strings":["Istituto Guido Castelnuovo, Universit\u00e0 di Roma, Piazzale Aldo Moro 4, 00185 Rome, Italy"],"affiliations":[{"raw_affiliation_string":"Istituto Guido Castelnuovo, Universit\u00e0 di Roma, Piazzale Aldo Moro 4, 00185 Rome, Italy","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074793077"],"corresponding_institution_ids":["https://openalex.org/I4210162062"],"apc_list":{"value":3160,"currency":"USD","value_usd":3160},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12619756,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":"4","first_page":"352","last_page":"361"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8839353919029236},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7702293992042542},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.7021821141242981},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6267521381378174},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.4246100187301636},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33845987915992737},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.281826376914978},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22457417845726013}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8839353919029236},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7702293992042542},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.7021821141242981},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6267521381378174},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.4246100187301636},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33845987915992737},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.281826376914978},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22457417845726013}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0743-7315(85)90019-x","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0743-7315(85)90019-x","pdf_url":null,"source":{"id":"https://openalex.org/S157146593","display_name":"Journal of Parallel and Distributed Computing","issn_l":"0743-7315","issn":["0743-7315","1096-0848"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Parallel and Distributed Computing","raw_type":"journal-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/386709","is_oa":false,"landing_page_url":"http://hdl.handle.net/11573/386709","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1494104063","https://openalex.org/W1964718922","https://openalex.org/W2007280161","https://openalex.org/W2041329792","https://openalex.org/W2066782398","https://openalex.org/W2067002313","https://openalex.org/W2104508180","https://openalex.org/W2149977307","https://openalex.org/W2177947168","https://openalex.org/W6660682229","https://openalex.org/W6667001608","https://openalex.org/W6667208009","https://openalex.org/W6685986965"],"related_works":["https://openalex.org/W2050076411","https://openalex.org/W4226119751","https://openalex.org/W1542183432","https://openalex.org/W2360686363","https://openalex.org/W2001478969","https://openalex.org/W1900787600","https://openalex.org/W2136552483","https://openalex.org/W2166954426","https://openalex.org/W4383684213","https://openalex.org/W2045082154"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
